Diagrammer needs flag to allow passing in annotations

[chick]

Some diagrams aren't generated correctly if annotations are not included. This can be caused by DontTouch annotations being not included, cause elements of the hierarchy to be removed

[chick]

Sample firrtl file

;buildInfoPackage: chisel3, version: 3.5-SNAPSHOT, scalaVersion: 2.12.13, sbtVersion: 1.5.2
circuit Foo : 
  module Baz : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 22:18]
    out <= r @[RegisterPresetTest.scala 25:7]
    
  module Baz_1 : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 22:18]
    out <= r @[RegisterPresetTest.scala 25:7]
    
  module Bar : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    inst sub3 of Baz @[RegisterPresetTest.scala 34:20]
    sub3.clock <= clock
    sub3.reset <= reset
    inst sub4 of Baz_1 @[RegisterPresetTest.scala 36:20]
    sub4.clock <= clock
    sub4.reset <= reset
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 40:18]
    node _out_T = add(r, sub3.out) @[RegisterPresetTest.scala 43:12]
    node _out_T_1 = tail(_out_T, 1) @[RegisterPresetTest.scala 43:12]
    node _out_T_2 = add(_out_T_1, sub4.out) @[RegisterPresetTest.scala 43:24]
    node _out_T_3 = tail(_out_T_2, 1) @[RegisterPresetTest.scala 43:24]
    out <= _out_T_3 @[RegisterPresetTest.scala 43:7]
    
  module Baz_2 : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 22:18]
    out <= r @[RegisterPresetTest.scala 25:7]
    
  module Baz_3 : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 22:18]
    out <= r @[RegisterPresetTest.scala 25:7]
    
  module Bar_1 : 
    input clock : Clock
    input reset : AsyncReset
    output out : UInt<8>
    
    inst sub3 of Baz_2 @[RegisterPresetTest.scala 34:20]
    sub3.clock <= clock
    sub3.reset <= reset
    inst sub4 of Baz_3 @[RegisterPresetTest.scala 36:20]
    sub4.clock <= clock
    sub4.reset <= reset
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 40:18]
    node _out_T = add(r, sub3.out) @[RegisterPresetTest.scala 43:12]
    node _out_T_1 = tail(_out_T, 1) @[RegisterPresetTest.scala 43:12]
    node _out_T_2 = add(_out_T_1, sub4.out) @[RegisterPresetTest.scala 43:24]
    node _out_T_3 = tail(_out_T_2, 1) @[RegisterPresetTest.scala 43:24]
    out <= _out_T_3 @[RegisterPresetTest.scala 43:7]
    
  module Foo : 
    input clock : Clock
    input reset : AsyncReset
    output out1 : UInt<8>
    output out2 : UInt<8>
    output out3 : UInt<8>
    
    reg r : UInt<8>, clock with : (reset => (reset, UInt<8>("h07b"))) @[RegisterPresetTest.scala 55:18]
    inst sub1 of Bar @[RegisterPresetTest.scala 59:22]
    sub1.clock <= clock
    sub1.reset <= reset
    out2 <= sub1.out @[RegisterPresetTest.scala 60:10]
    inst sub2 of Bar_1 @[RegisterPresetTest.scala 62:22]
    sub2.clock <= clock
    sub2.reset <= reset
    out3 <= sub2.out @[RegisterPresetTest.scala 63:10]
    out1 <= r @[RegisterPresetTest.scala 69:8]
    

[chick]

Annotations example for above firrtl

[
  {
    "class":"firrtl.stage.FirrtlFileAnnotation",
    "file":"test_run_dir/registers_with_presets_in_submodules_should_get_set_at_beginning/Foo.lo.fir"
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Baz",
    "duplicate":"~Foo|Foo/sub1:Bar/sub3:Baz",
    "index":0.0
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Baz_1",
    "duplicate":"~Foo|Foo/sub1:Bar/sub4:Baz",
    "index":0.16666666666666666
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Bar",
    "duplicate":"~Foo|Foo/sub1:Bar",
    "index":0.3333333333333333
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Baz_2",
    "duplicate":"~Foo|Foo/sub2:Bar/sub3:Baz",
    "index":0.5
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Baz_3",
    "duplicate":"~Foo|Foo/sub2:Bar/sub4:Baz",
    "index":0.6666666666666666
  },
  {
    "class":"firrtl.transforms.DedupedResult",
    "original":"~Foo|Bar_1",
    "duplicate":"~Foo|Foo/sub2:Bar",
    "index":0.8333333333333334
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.LowFirrtlEmitter"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub2:Bar>r"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub2:Bar/sub4:Baz>r"
  },
  {
    "class":"firrtl.annotations.PresetAnnotation",
    "target":"~Foo|Foo/sub2:Bar/sub4:Baz>reset"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub2:Bar/sub3:Baz>r"
  },
  {
    "class":"firrtl.annotations.PresetAnnotation",
    "target":"~Foo|Foo/sub2:Bar>reset"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub1:Bar>r"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub1:Bar/sub4:Baz>r"
  },
  {
    "class":"firrtl.annotations.PresetAnnotation",
    "target":"~Foo|Foo/sub1:Bar/sub4:Baz>reset"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo/sub1:Bar/sub3:Baz>r"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Foo>r"
  },
  {
    "class":"firrtl.annotations.PresetAnnotation",
    "target":"~Foo|Foo>reset"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"test_run_dir/registers_with_presets_in_submodules_should_get_set_at_beginning"
  }
]