AMD CPU support

[petersulyok]

This issue is the placeholder for the discussion about this new feature started in issue #22 .

Previous comments from @staaled:

1. [Feature request] Add support to Supermicro M12SWA-TF #22 (comment)
2. [Feature request] Add support to Supermicro M12SWA-TF #22 (comment)

[petersulyok]

Hi @staaled, nice investigation here, thanks a lot for that. Still I try to understand the connection between the number of the CPUs (count=2 configuration parameters) and PCI entities listed in your example:

lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:18.3 -> ../../../../devices/pci0000:00/0000:00:18.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:19.3 -> ../../../../devices/pci0000:00/0000:00:19.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1a.3 -> ../../../../devices/pci0000:00/0000:00:1a.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1b.3 -> ../../../../devices/pci0000:00/0000:00:1b.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1c.3 -> ../../../../devices/pci0000:00/0000:00:1c.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1d.3 -> ../../../../devices/pci0000:00/0000:00:1d.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1e.3 -> ../../../../devices/pci0000:00/0000:00:1e.3
lrwxrwxrwx  1 root root    0 Jul  3 12:08 0000:00:1f.3 -> ../../../../devices/pci0000:00/0000:00:1f.3

In my mind we have to identify 1 HWMON file per CPU. How can we select 2 of these?

[staaled]

For zen1 generation CPUs it seems like they don't have more than a Tctl value for each core complex, which I guess means 4x complexes per socket. At least for the 32 core CPUs...

However, since the results I posted was from a 5.4 kernel, this might have changed, see https://www.phoronix.com/news/Linux-k10temp-debugfs etc...

[petersulyok]

Version 3.0 has been released with some recommendations for the AMD users in the README.md. But still automatic identification of the HWMON files are not there.