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core
core
 
 
processor_templates
processor_templates
 
 
system_integration
system_integration
 
 
test_setups
test_setups
 
 
README.md
README.md
 
 

README.md

Hardware RTL Sources

  • core: This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. When creating a new synthesis/simulation project make sure that all *.vhd files from this folder are added to a new design library called neorv32. The processor's top entity is neorv32_top.vhd.

Important

The sub-folder core/mem contains the platform-agnostic VHDL architectures of the processor-internal memories (IMEM & DMEM). Make sure to add one of these modules for each memory to the project's HDL file list. These default files can also be replaced by optimized platform-specific memory modules.

  • processor_templates: Contains pre-configured "SoC" templates that instantiate the processor's top entity from core. These templates can be instantiated directly within a FPGA-specific board wrapper.

  • system_integration: Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default processor top entity from core, but featuring a different interface.

  • test_setups: Minimal processor test setups (FPGA- and board-independent. See the folder's README for more information. Note that these test setups are used in the NEORV32 User Guide.