Synchronous and Asynchronous FIFO with AXI interface
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Updated
Nov 20, 2019 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
AXI4 and AXI4-Lite interface definitions
Network on Chip Implementation written in SytemVerilog
VeeR EH1 core
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
Common SystemVerilog RTL modules for RgGen
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
VeeR EL2 Core
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