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76 public repositories
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Chisel Designer's Library
Updated
Dec 12, 2016
Scala
Superscalar OoO RISCV processor written in Chisel
Updated
Jan 3, 2017
Scala
RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA
Updated
Oct 15, 2017
Scala
Updated
Dec 3, 2017
Scala
Collection of utilities to simplify FPGA accelerator design
Updated
Apr 12, 2019
Scala
This is my graduation project, a simple processor soft core, which implements RV32I ISA.
Updated
May 23, 2019
Scala
Make writing trivial inst{ruction,rumentation}s for RocketChip as simple as writing the C code
Updated
Jul 27, 2019
Scala
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
Updated
Jul 30, 2019
Scala
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
Updated
Jul 30, 2019
Scala
Boilerplate for a full project with chisel and a DE0 Nano
Updated
Dec 30, 2019
Scala
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Updated
Jan 23, 2020
Scala
A template Chisel project for the DE1SOC FPGA board
Updated
Feb 13, 2020
Scala
Updated
Jul 1, 2020
Scala
[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
Updated
Oct 8, 2020
Scala
A lightweight Ethernet MAC Controller IP for FPGA prototyping
Updated
Oct 19, 2020
Scala
Updated
Jan 9, 2021
Scala
Updated
Jan 9, 2021
Scala
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Updated
Apr 11, 2021
Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
Updated
Apr 13, 2021
Scala
mini risc-v kernel by Chisel 3
Updated
Jul 31, 2021
Scala
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