yosys
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A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project
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Aug 2, 2021 - Python
A nextpnr arch definition for the TuringTumble board game.
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Nov 5, 2022 - Verilog
Example of how to get started with olofk/fusesoc.
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Jul 25, 2021 - Python
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
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Jul 11, 2024 - VHDL
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
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Aug 2, 2023 - Makefile
Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
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Apr 26, 2019 - C++
Verilog implementations of different simple tasks
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Oct 10, 2022 - Verilog
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
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Jul 3, 2024 - Verilog
Basic counter example in verilog for Tang Nano 20k using Yosys, Nextpnr and openFPGALoader.
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Jun 28, 2024 - Verilog
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