stm32: usb: STM32U5 HS-USB peripheral

[sageve]

Hi

I try getting the USB high speed peripheral of the STM32U5A5 to work. For me, it seems it is not supported, yet. What I have done so far:

1. Take the cdc_acm example
2. Add an overlay for the nucleo_u5a5zj_q board

/ {
    otghs_phy: otghs_phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

    soc {
		usbotg_hs: usb@42040000 {
			compatible = "st,stm32-otghs";
			reg = <0x42040000 0x20000>;
			interrupts = <73 0>;
			interrupt-names = "otghs";
			num-bidir-endpoints = <9>;
			ram-size = <4096>;
			maximum-speed = "high-speed";
                        /* USBPHYC_SEL: 0: HSE; 1: PLL1_P, 2: HSE/2; 3: PLL1_P/2 */
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x0000C000>,
			         <&rcc STM32_SRC_HSE USBPHYC_SEL(0)>, /* see ref manual 11.8.47 */
			         /* udc driver DOES NOT activate following clocks. */
				 <&rcc STM32_CLOCK_BUS_APB3 0x00000002>; /* SYSCFG_CLK */
			phys = <&otghs_phy>;
			status = "disabled";
		};
	};
};

&clk_hse {
    status = "okay";
    clock-frequency = <DT_FREQ_M(16)>;
};

&pll1 {
    clocks = <&clk_hse>;
    div-m = < 4 >;
    div-p = < 20 >; /* 16 MHz PLL1_P, not used */
};

zephyr_udc0: &usbotg_hs {
	pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
	pinctrl-names = "default";
	status = "okay";

    cdc_acm_uart0 {
		compatible = "zephyr,cdc-acm-uart";
	};
};

Build fails:

zephyr/drivers/usb/device/usb_dc_stm32.c:281:43: error: 'LL_AHB1_GRP1_PERIPH_OTGHSULPI' undeclared (first use in this function);

3. After modifying the usb_dc_stm32.c driver fixing the clock/phy enable setup, it gets stuck in the USB_CoreReset function.

Link to repo: https://github.com/sageve/zephyr-minimal/tree/hs-usb
Modifications in usb_dc_stm32.c: main...sageve:zephyr:hs-usb

Either my device tree and/or my changes in usb_dc_stm32.c are wrong or there is a lot more missing in order to get the high speed phy work. Further debugging without knowing what's actually implemented, seems like a lot of work for me.

@erwango Can you or one of your members give me a hint?

Thank you.

[erwango]

@marwaiehm-st Would you be able to help ?

[marwaiehm-st]

You should modify the value of div-m (div-m = < 2 >) because with "div-m=4" the value PLL1_P is 8 MHZ , you need 16 MHZ for the OTG_HS clock.

[sageve]

The overlay might be misleading. I have only made changes that differ from the nucleo dts. The pll node is merged to:

pll1: pll: pll {
			#clock-cells = < 0x0 >;
			compatible = "st,stm32u5-pll-clock";
			status = "okay";
			div-m = < 0x4 >;
			mul-n = < 0x50 >;
			div-q = < 0x2 >;
			div-r = < 0x2 >;
			clocks = < &clk_hse >;
			div-p = < 0x14 >;
			phandle = < 0x2 >;
		};

PLL_1P equals 16 MHz (HSE) / 4 * 80 / 20 = 16 MHz. However PLL_1P is not used. The line <&rcc STM32_SRC_HSE USBPHYC_SEL(0)> should set the clock source to 16 MHz HSE, but it's also the default value.

In addition to that, I added setup code to the usb_dc_stm32_clock_enable function as you can see in my zephyr fork. There I

• enable the SYSCFG clock
• enable the USBPHY clock
• disable USBPHY clock stop in sleep modes
• set phy clock frequency to 16 MHz
• set the OTGHSPHYTUNER2 bits as describen in the ref manual
• enable the hs phy

I have also checked that all this values are written into registers.