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Curtis Instruments, Inc.
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Muzammal Ahmed
*** Strategic Considerations for Work Models in Firmware/Hardware Engineering *** In the context of firmware/hardware development, the choice of work environment is not just a matter of preference but a strategic decision that impacts productivity. I am a strong proponent of onsite work. This model facilitates direct interaction with hardware prototypes, real-time debugging, and the synchronous collaboration essential for iterative development cycles. These elements are critical in firmware/hardware engineering, where integration with physical devices and immediate feedback on system performance are supreme. Acknowledging the shift towards more flexible work arrangements, a hybrid model can be considered a viable alternative. This approach allows for the rigorous discipline required for development and system validation phases. The key to succeeding in this discipline is to ensure that everyone committed to hybrid schedule adheres to it. However, a fully remote model is severely limited for firmware/hardware engineering. The absence of immediate access to test equipment and the latency in remote hardware access setups can significantly decelerate the development and troubleshooting processes. Moreover, the spontaneous, often unexpected, technical exchanges that catalyze breakthroughs in firmware/hardware optimization and innovation are markedly reduced in remote settings. In conclusion, while flexibility remains a significant factor in modern workforce management, the unique demands of firmware/hardware engineering make it essential to preserve a substantial degree of onsite presence. Ensuring regular onsite engagement helps maintain the high standards of technical rigor and collaborative innovation that firmware/hardware development demands.
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Suresh V.
16 of 28 #job #openings on 5/14 ✴️ #software engineer ✴️ Conduit - Software for Warehouses #checkitout and #share. #follow Suresh V. for #cool opportunities and ideas! #opportunity #usajobs #usa #hiring #hiringnow #open #jobsearch #reshare #engineeringjobs #engineering #givingback #spreadtheword #connectandgrow #repost
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Yuri Panchul
Can Gowin beat Xilinx and Altera in the educational market? Gowin Semiconductor is at the Sensors Converge exhibition in Santa Clara today. I went to their booth yesterday and met the team: CEO Jason Zhu, sales, marketing and application engineers. We discussed the topic of the educational boards used for EE classes, such as 6.111 at the Massachusetts Institute of Technology (MIT). Every ASIC designer working at Samsung, Apple, NVidia and similar companies has taken a similar class back in school. It is not possible to train an RTL designer using a Verilog simulator only. In order to develop intuition in static timing analysis (STA) and how many resources are inferred for a given RTL code, a student has to either use FPGA or ASIC synthesis, and with FPGA, he also gets the benefit of working with an actual design. This fact makes educational FPGA boards a critical technology for any country’s high-tech workforce development, a topic that now concerns even the US Government, as I heard at the Design Automation Conference in San Francisco a day earlier. Gowin has an opportunity to grab this market from Xilinx and Altera. For two reasons: 1) price and 2) synthesis speed. Synthesis in Gowin IDE runs an order of magnitude faster than on Xilinx Vivado. A design of a graphical game with sprites is synthesized in 209 seconds with Xilinx Vivado and just 22 seconds with Gowin. Altera is in the middle: 56 seconds. If you are a student working on a project, this is a big deal, since you run synthesis with every code change, and if you do this 20 times a day, waiting minutes instead of seconds is annoying, and Gowin IDE speed gives a totally different user experience. Now let’s discuss what do we need for an educational FPGA board - https://lnkd.in/gpxUCnrr
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15 Comments -
Phoenix Jobs
#hiring *Senior Principal FPGA Design Engineer (Onsite)*, Phoenix, *United States*, fulltime #jobs #jobseekers #careers #Phoenixjobs #Arizonajobs #Engineering *Apply*: https://lnkd.in/grvpcJfR Date Posted:2024-02-05Country:United States of AmericaLocation:AZ852: RMS AP Bldg M East Hermans Road Building M02, Tucson, AZ, 85756 USAPosition Role Type:OnsiteAt Raytheon, you have the opportunity to try new things and make a bigger difference across a broader end-to-end solution, a richer technology and product set, an expanded range of disciplines, a growing global footprint and a more diverse team of colleagues and customers.Job Summary:The Effector Digital Products (EDP) department develops electronics for our weapon system products. We engage at the outset of the weapon system development and follow our designs through deployment. Our products are deployed all over the world, from the ground to exoatmospheric environments and into space. We are responsible for the architecture, design, and documentation of deliverable FPGA embedded processing at RMD.In this role you will lead develop of FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi. Designs commonly support the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers collaborate with circuit card designers and systems engineers to develop requirements, architecture, modeling of algorithms, partitioning, code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies.Design support is expected from requirements definition through production release. Design documentation and configuration management are required.Responsibilities to Anticipate:• Leader of FPGA-based systems architecture, and design to include determination of parts, interfaces, and Concept of Operations (CONOPS). Delivering quality releases from initial proof of concept up through production.• Establish processes and operational plans for a project.• Independently drive projects and execute to program schedules on time and budget.• May lead large integrated or cross product teams on moderate to large multi-year programs.• Design, develop, implement and verify highly complex configurable logic solutions for products that significantly improves on an existing product.• Solve problems that are numerous and typically undefined where information is difficult to obtain. • Conducts extensive investigation to understand root cause of problems.• Communicates with parties within and outside of own function which would include customers, vendors, and executive leadership.• Translate system-level requirements into FPGA requirements.• Create complete documentation including requirements, verification plan, and
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Dinesh V.
Reads of the week Engineering — Tesla's wafer-sized Dojo processor is in production — 25 chips combined into one https://lnkd.in/gQ7E4yjf PoC to demonstrate root permission hijacking by exploiting “systemd-run” (https://lnkd.in/gwjv6BiE): https://lnkd.in/guvb-6rk Releases Distribution Changes: https://lnkd.in/gdUFXCj2 Repos — Slice and dice log files on the command line: https://lnkd.in/gxsamgEu Self Development — My Love/Hate Relationship with Repetition: https://lnkd.in/gJJCQQ5P Nice Reads — The New Zealand city with a labyrinth of underground caves: https://lnkd.in/g5ZUfF5q Microsoft’s OpenAI investment was triggered by Google fears, emails reveal: https://lnkd.in/g4tPuwfj Tesla staff say firm's entire Supercharger team fired: https://lnkd.in/gfFGvtcp
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Stephen Botelho
Senior Diagnostic Engineer @ Doble Engineering - Low-level / CPU-level hardware diagnostics: To apply: https://lnkd.in/eZY3SbfC A hardware diagnostic engineer focused on board-level and bare-metal diagnostics would need an advanced and highly specialized skill set: Hardware Expertise: Component-Level Understanding: In-depth knowledge of semiconductor devices, including transistors, diodes, integrated circuits, and passive components, with a focus on their behavior and interactions in complex circuits. Schematic Analysis and PCB Design: Proficient in analyzing detailed circuit schematics and PCB layouts using tools such as Altium Designer, Cadence Allegro, or KiCad to diagnose connectivity and design issues. Microarchitectures: Extensive familiarity with various microcontroller and microprocessor architectures (ARM, x86, RISC-V) and their low-level operation. Low-Level Software Proficiency: Assembly Language Programming: Expertise in writing and debugging assembly code for different architectures, enabling direct hardware manipulation and control. C code. Registry File Manipulation: Deep understanding of registry file structures, particularly in real-time operating systems (RTOS) and embedded Linux environments, and the ability to modify and create registry entries to control hardware configurations. Device Driver Development: Proficient in writing and debugging device drivers for various peripherals and interfaces, ensuring seamless integration and communication between hardware and software. Diagnostic and Testing Proficiencies: Advanced Oscilloscope and Logic Analyzer Usage: Mastery in utilizing oscilloscopes and logic analyzers to capture, analyze, and interpret high-speed signals and bus transactions at the board level. In-Circuit and Functional Testing: Proficient in in-circuit testing (ICT) and functional testing methodologies to verify and validate hardware functionality down to the pin level. Analytical and Problem-Solving Skills: Advanced Troubleshooting Techniques: Employing systematic and methodical approaches to isolate and rectify hardware faults, utilizing root cause analysis and fault tree analysis (FTA) methodologies. Power Integrity and Thermal Analysis: Expertise in analyzing and mitigating power integrity and thermal management issues at the board level, ensuring stable and reliable operation under various conditions. Problem Debugging and Isolation: Skilled in identifying and isolating problems through methodical debugging techniques, ensuring accurate fault detection and resolution. Board Bring-Up: Initial Hardware Testing: Experience in initial hardware bring-up, including validating power supply sequences, clock initialization, and memory testing.
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Caleb Vainikka
There's no magic in hardware engineering. There's no secret book that defines the path to success for every project. Many young engineers ask me, how would you design this? Or this? Or that? I'm happy to give my recommendations on what they should do in each instance. But my opinion, thoughts, and recommendations are my own. There's no gatekeeper to define if you do X, Y, and/or Z then your designs will be successful. Here a few guiding principal for design engineers working with industrial designers. (note that these are not technical skills) Develop a bias towards action. Don't overanalyze every decision. Avoid the urge to simulate every decision. Build and test as soon as possible, using real materials, in the real world. Think outside the box: the 'right' solution is the solution that solves the most problems, for the whole team. Don't focus on only mechanical engineering. We might not always land on the most efficient solution. Don't get hung up on efficiency with every decision. Put some extra plastic in there. Add a few extra parts. Be easy to work with. Flexibility in design engineering goes a long way. Try to be helpful. Don't dig in your heels and try to prove that your idea is best. Learn about business goals, don't just focus on design goals. Develop rationale or justification for your ideas if you feel strongly about them. If your idea is critical to program success, then develop a stronger business case for making the decision, don't just increase your volume in the argument. Have some humility. You're not the smartest engineer in the room. Or even if you are, showing humility and admitting that others might be right is a super power. Be honest. Detach from the outcome. You're a critical piece of the project, but you're also just an engineer on the project. Engineering is generally a cost center, not a profit center. Build value in your involvement by understanding how your costs affect the project goals. Don't try to convince the industrial designers that they can't build their dreams. Try to understand what they're trying to do. How are they trying to help the user? #design I love working 1:1 with industrial designers. If you're an industrial designer, looking for an experienced mechanical engineering resource that believes in you, one that encourages your creativity, and that will help you push your vision through the complications of manufacturing, let's connect on LinkedIn, I'd love to chat!
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Jeffrey Sutherland
Widespread deployment of AI may be in trouble. John Loeffler, writing on the web site Techradar (https://lnkd.in/gDHWKEjU) published one of the more thoughtful assessments of Nvidia CEO Jensen Huang's keynote speech June 3 at Taipei's Computex 2024. But I think John need not be overly concerned about the speed of deployment of AI. I attended Computex this year and the hype surrounding the coming of AI seems significantly out of touch with a simple reality: there's not enough electrical generating or grid transmission capacity to run all the proposed deployments of new data centers, or "AI factories". Virtually lost among all the hype over Nvidia's new Blackwell GPU is the massive amount of power required to run it. Can someone who was there help fact check this for me? Marc Hamilton from Nvidia while showing an example of a dual Blackwell server blade said with a straight face that a server rack of 72 Blackwell processors required 100KW, along with liquid cooling. I thought I heard wrong at first but then started doing some back of the envelope math. If every Blackwell GPU was running at full tilt in a rack the peak energy consumption needed for the rack plus cooling system just might approach 100KW. Now how many racks will be in a "AI factory"? It will need its own multi-megawatt power plant out back just to run the place. Some other fun facts about data center power consumption today: 30% of the electricity generated in Ireland goes to run data centers there. In 2022 data centers worldwide consumed 460 TeraWatt/hrs. By 2026 data centers at current deployment rates will need 1050 TeraWatt/hrs annually. That's more energy than the entire country of Japan uses today. Where is all this power going to come from? Jensen Huang has proposed building a large AI factory here in Taiwan, where we barely have enough energy in the summer to run all our air conditioners. How is that going to work?
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Sanjay Adhikari
Starting ABCDE again for new evening batch tomorrow. Live sessions are more effective as compared to recorded stuff. I adjusted my schedule for working embedded system professionals. * 8:45PM - 9:45PM for those who don't get time during weekends. * Separate batches on Saturday and Sunday Morning Just finished regular Coding skills exercise with Premium club members. Learn in an environment with experienced embedded system professional and be ahead in competition always .... If your target is big , you need to come out of comfort zone. Learn from various sources until you get expertise and can face interviews with full confidence. Just learn it ... Have a Great Day ! #embedkari #embeddedsystem #opentowork #freshers #firmware
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Gaurav Jain
Some mind-blowing 🤯 numbers from Corsair 🛫 by d-Matrix! 9600 TFLOPS 2GB of SRAM 150TB/s memory bandwidth 1TB/s D2D bandwidth For some time, the industry has recognized the imperative for comprehensive, industry-wide initiatives in #hardware, #software, and end-to-end systems to deliver efficient and high-performance AI experiences. The recent surge in #generativeAI has only heightened this urgency, necessitating immediate action. Real-time experiences in downstream tasks such as #textgeneration for Chatbots, Question Answering, and Code Copilots are often constrained by the absence of systems capable of serving these use cases in a cost-effective, low-latency, and energy-efficient manner. Recent releases such as #llama3 by Meta and #phi-3 by Microsoft underscore how organizations are increasingly favoring smaller models pre-trained on well-curated datasets, enabling developers to provide real-time #generativeAI experiences to users while minimizing #inference-serving costs. Corsair by d-Matrix represents a giant leap in this direction. The figures presented above are poised to revolutionize the economics of single-rack GenAI inference by substantially enhancing interactivity metrics (tokens per second per user) and perf-TCO metrics ($ per token). To learn more about Corsair and d-Matrix, visit us at TSMC's North America Technology Symposium on 24th April 2024. #generativeAI #llms #hardware #dmatrix #tsmc
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Aaron Wei-Rong Lee
How breathtaking it is, we are now standing at the turning point of the industrial revolution: “If you run a factory, your throughput directly correlates to your revenue, the quality of service, the number of people who can use your service. We are now in a world where datacenter throughput utilization is vitally important. It was important in the past, but people don’t measure it. Today, every parameter is measured. When something is a factory, its operations directly correlate to the financial performance of the company,” Jensen Huang (COMPUTEX 2024) Watch the insightful keynote by Jensen Huang at COMPUTEX 2024: [Link to the video](https://lnkd.in/dB9aj2qr) #computex2024
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Brad Butler
Sometimes you learn a thing or two from corporate publications... Cadence has reduced its GHG footprint 33% since 2019, with a goal of reaching net zero by 2040. My first thought was: 2040? We're a software company - we don't own vehicle fleets or power plants. We do operate data centers and offices, and we travel. But how hard could it be for a software company to get to net zero? I learned that this goal encompasses Scope 1 (direct), Scope 2 (operations), and Scope 3 (value chain) GHG emissions, and what those terms mean. For scope 1 & 2 -- the emissions that we control directly -- we're basically already there. 99% of our net emissions fall into Scope 3. Scope 3 consists of upstream (what we buy) and downstream (what our customers do with what we sell), and are much harder to mitigate than our own operations. Reducing upstream emissions means engaging with suppliers to understand their operations, and making procurement choices that steer you toward net-zero. That includes everything from servers to office furniture to airline tickets. Reducing downstream emissions is still more complex - it means engaging customers to understand how they are using our products, and what their mix of energy is. Customers' progress toward their own sustainability goals help us achieve ours. This was a good lesson for some light Monday reading... #CadenceMissionSustainable #WeAreCadence https://lnkd.in/esswUYYh
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5 Comments -
Mark Rawson
We often don't fully appreciate the capabilities of today's modern multi-core processors in our normal everyday work. One great example of where they really excel is building embedded linux #yocto #openembedded. Check out this screen shot of a 13th generation #intel core processor running 22 build tasks simultaneously. Combined with a couple of very fast PCIe Gen4 x4 M.2 solid state drives and 64GB of DDR5 memory, it built an arm64 core-image-minimal image from scratch in just under 20 minutes.
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Horng Neng Ong
🚀 Excited to share that I've just completed the "Predict Bike Sharing Demand with AutoGluon" project! 🚲📈 This project was an incredible journey into the world of automated machine learning with AutoGluon. I had the opportunity to explore the power of automation in streamlining complex machine learning workflows. Leveraging advanced machine learning techniques, I explored feature engineering, hyperparameter tuning, and the power of automation to optimize model performance. 🔍 Default Model: Initially, I trained a baseline model without any preprocessing or tuning, serving as a benchmark to assess the raw dataset's performance. 📊 Model with Additional Features: Through in-depth exploratory data analysis, I identified opportunities to enhance model performance by creating additional features. These features captured nuanced patterns in the data, resulting in a significant improvement in predictive accuracy. 🔥 Model with Hyperparameter Tuning: Fine-tuning the model's hyperparameters further optimized its performance. By systematically searching for the optimal combination of hyperparameters, I achieved even better results, ensuring the model operates at its peak performance level. Delighted to share that my efforts culminated in a Kaggle score of 0.46986, showcasing the effectiveness of AutoGluon in streamlining the ML workflow. Looking forward to applying these insights to future projects! #AWS #Udacity #AutoGluon #MachineLearning #DataScience #BikeSharingDemand #KaggleChallenge #FeatureEngineering #HyperparameterTuning #Automation #MLWorkflow 📊 #AWS #Udacity #AIML #AutoGluon
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