Design Verification Engineer
Position: Design Verification Engineer
Location: San Jose/Austin (Onsite/Hybrid)
Position Overview:
- 5+ years of relevant experience in Design Verification.
- Experience with System Verilog and UVM is a must.
- Strong experience in testbench development such as UVM methodology.
- Knowledge of GPU, experience with Shader, Texture, or Memory System a plus.
Responsibilities:
- Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
- Triage regression failures and make testbench updates.
- Generate and run Testcases on logic simulation models.
- Closely work with Architects and RTL designers.
- Drive Functional Coverage and Code coverage to closure.
Education:
Bachelors Degree in related field.
-
Seniority level
Mid-Senior level -
Employment type
Contract -
Job function
Engineering -
Industries
Semiconductor Manufacturing
Referrals increase your chances of interviewing at ACL Digital by 2x
See who you knowGet notified about new Design Verification Engineer jobs in San Jose, CA.
Sign in to create job alertSimilar jobs
People also viewed
-
Electrical Engineer
Electrical Engineer
-
Electrical Engineer
Electrical Engineer
-
Transmission and Distribution Electrical Engineer
Transmission and Distribution Electrical Engineer
-
Electrical Engineer
Electrical Engineer
-
Junior Electrical Engineer
Junior Electrical Engineer
-
Entry to Junior Level Electrical Engineer
Entry to Junior Level Electrical Engineer
-
Electrical Engineer
Electrical Engineer
-
Electrical Designers and Engineers
Electrical Designers and Engineers
-
Electrical Project Engineer
Electrical Project Engineer
-
Electrical Engineer
Electrical Engineer
Looking for a job?
Visit the Career Advice Hub to see tips on interviewing and resume writing.
View Career Advice Hub