Addwiser

Design Verification Engineer

Addwiser New York, NY
Addwiser

Design Verification Engineer

Addwiser New York, NY
4 months ago 53 applicants

See who Addwiser has hired for this role

Key Responsibilities

  • Lead Formal verification.
  • Create UVM/System Verilog based testbenches and tests.
  • Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
  • Define verification plan, and provide technical direction to execution teams
  • Make sure that design is bug free.
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.

Preferred Experience

  • Formal verification expertise.
  • Firmware experience.
  • IO/PHY knowledge.
  • Excellent communication, management, and presentation skills.

Academic Credentials

  • Bachelor’s or Master’s degree in Electronics.

  • Seniority level

    Mid-Senior level

  • Employment type

    Full-time

  • Job function

    Engineering and Information Technology

  • Industries

    Appliances, Electrical, and Electronics Manufacturing and Semiconductor Manufacturing

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