FIRMWARE ENGINEER 3
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Description
Title: Design Verification Engineer
Roles & Responsibilities
Additional Details
Title: Design Verification Engineer
Roles & Responsibilities
- Responsibilities includes starting from testplanning to closing verification using coverage metrics.
- Involves testbench development from scratch or modification to existing testbench infrastructure for verifying new features.
- Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model.
- Directed/constrained random test generation, failure analysis and resolution, coverage analysis.
- Debugging failures, bug tracking, and analyze and close coverage.
- Advanced knowledge of HVL methodology (UVM).
- Expertise in HVL and HDL (SystemVerilog, Verilog).
- Experience defining coverage space and writing coverage model.
- Experience with SystemVerilog Assertion (SVA) is a plus.
- Team player with excellent communication skills and the desire to take on diverse challenges.
- Experience writing scripts in languages such as Perl/Python.
- Solid verification skills in problem solving, constrained random testing, and debugging.
- Experience with Veloce or other HW acclerators and Formal is a plus.
Additional Details
- Pre-identified worker (First Name, Last Name) & Supplier Name : (No Value)
- Job Posting Type : Agency Recruited Worker Required
- Worker Legal Name (For Manager Sourced Only) : (No Value)
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Seniority level
Entry level -
Employment type
Full-time -
Job function
Engineering and Information Technology -
Industries
Information Technology & Services
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