Applied Materials’ Post

Good, quick read that lays out interconnect challenges as copper reaches the end of the road: Beyond Backside Power: Scaling Chips to 2nm and Beyond Also Requires Frontside Wiring Innovations. It's been 3 years since Applied introduced a new way to extend copper with improvements in PVD liners. Interconnect is again the big limiter to scaling further. No solutions here, but intriguing is Dr. Naik's promise: "At next week’s SEMICON West, Applied Materials will unveil innovations designed to extend copper to the 2nm node and below." I can't wait to see what they have to say. https://lnkd.in/gY5gqNBW

"Traditional memory technologies face limitations in terms of speed, scalability, and power consumption, making them unsuitable for future data-intensive applications. Ferroelectric memory has garnered immense interest in recent years due to its potential for non-volatile storage, enabling data retention even when the power is turned off. The development of two-dimensional (2D) van der Waals material α-In2Se3 has also opened new opportunities for advancing memory technologies. Interestingly, ferroelectric memory takes a giant step forward by incorporating the remarkable properties of α-In2Se3. It is renowned for high carrier mobility, tunable bandgap, and strong ferroelectric properties at the atomic level, making it ideal for high-speed memory applications." #datastorage #semiconductormemory

Most experienced chip designers will agree that, until recently, the industry’s methods to address thermal challenges have been less than systematic, relying more on engineer’s gut feel. This can, in most cases, lead to under/over-design. With momentum picking up around heterogeneous integration with 2.5D chiplet-based Systems on Package (SoP), we are hitting a point where heat dissipation can limit performance scaling. Recently, I came across an intriguing study that leverages in-package wireless technology to mitigate thermal bottlenecks in 2.5D chiplet-based SoPs. Micro antennas replace the need for interposers allowing low-latency/ high-throughput systems. Combining thermal modeling, with system-level simulation, this paper argues that thermal-aware task distribution across compute cores is now feasible (thanks to in-package wireless comms). This novel approach opens up a new frontier in chip design, offering a robust solution to a longstanding challenge. The implications for high-performance computing, data centers, and other thermally-constrained applications are significant. Solutions like these continue to push the envelope in semiconductor performance. I highly recommend diving into this study for those interested in the deep technical aspects. It’s a testament to the kind of innovative thinking that will drive our industry forward: https://lnkd.in/gN2kNzh8 #ChipDesign #WirelessTechnology #Innovation #ChipletTechnology

#Infineon Technologies recently introduced a new range of advanced power supply units (PSUs) specifically designed for AI data centers. These PSUs, ranging from 3 kW to 12 kW, leverage new semiconductor technologies to achieve extremely high efficiencies. https://lnkd.in/gRXpF-et #SEEDST #ICchip #electroniccomponents #Semiconductorindustry #electronics #semiconductor #supplychain #manufacturingtechnology #processtechnology #engineering #manufacturing #technology #computerchips #business #innovation #semiconductors #chips #chipmaker #foundry

Power optimization is key for unlocking the capabilities of today’s technology. Mythic’s Dave Fick shared that analog technologies are a crucial component in the quest for energy-efficient computing due to its exceptional information density, which significantly reduces the need for transistors and wires. Reducing additional components in a product’s design can drastically help thermal management, resulting in greater performances. Head to Semiconductor Engineering for more on the future of energy-efficient computing: https://bit.ly/3I1AtSE

Backside power delivery network (#BSPDN) is key in next generation #semiconductors! 👾Chip manufacturers have already announced its incorporation in their logic roadmaps. 🙋🏽♀️🙋 imec was the first to proposed this concept back in 2019 in collaboration with Arm. In this article, Julien Ryckaert (Vice President Logic Technologies at imec) highlights the potential of backside power delivery for high-performance computing and evaluates options for backside connectivity. 🤔💻 In our group, we take care of all #thinfilm material depositions to make the necessary buried power rails (BPRs), the nano-TSV’s (Through-Silicon Vias) and back-side interconnect metallizations. Let’s comeback from holidays 🏖️ stronger to de-congest that #BEOL! 💪🏼 Read more ⬇👇🏼 #BSPD #logicdevices #3Dintegration #semiconductorindustry #imec #nanotechnology #science #engineering

Rohm, a leading semiconductor manufacturer, has unveiled a groundbreaking operational amplifier designed specifically for industrial and consumer applications. The new amplifier, named LMR1002F-LB, features a unique 'zero-drift' architecture that sets it apart from other amplifiers in the market. The LMR1002F-LB boasts impressive specifications, with a maximum input offset of 9µV and 50nV/°C. These figures are significantly better than the typical values of 1µV and 15nV/°C found in other amplifiers. This exceptional performance ensures accurate and reliable operation in a wide range of applications. #electricalengineering #electronics #embedded #embeddedsystems #electrical Follow us on LinkedIn to get daily news: HardwareBee - Electronic News and Vendor Directory

More Complex than #Intel’s? #TSMC’s Super #PowerRail – Elevating Chip Performance through Advanced Power Delivery At TSMC’s North America Technology Symposium, per a report from TechNews, the semiconductor giant unveiled its #A16 process, designed to accommodate more transistors, enhance computational performance, and reduce power consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving faster and more efficient development of data center processors. As Moore’s Law progresses, transistors become smaller and denser, with an increasing number of stacked layers. It may require passing through 10 to 20 layers of stacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnections and power lines. When electrical signals travel downward, there is IR voltage drop, resulting in power loss. Check full insights via the link below https://lnkd.in/gaSqezk2

Will this finally will help making this direction in to HVM? Nanostructures Bring Gains for Phase Change Memory Lower voltage operation could open doors for the nonvolatile memory Engineers in the United States and Taiwan say they have demonstrated a promising new twist on nonvolatile memory that’s small enough, miserly when it comes to energy, and works at low enough voltage that it could boost the abilities of future processors. The device is a type of phase change memory, a class of memory that holds information in the form of resistance and changes that resistance by melting and reforming its own crystal structure. The crystal in question, called a nanocomposite superlattice, leads to an order of magnitude improvement in the amount of power needed to write a bit, according to research reported last week in Nature Communications. The engineers say this form of phase-change memory (PCRAM) would be particularly useful in future compute-in-memory schemes, which save energy in machine learning by moving less data between memory and processor. https://lnkd.in/dF2krTw8

Photonics has become integral to the semiconductor industry, bridging the gap for power, performance, and area (PPA) optimization. Learn more about how integrating photonic components into multi-die systems can offer another answer to greater demands for bandwidth, energy efficiency, and density of next-generation chips. https://ow.ly/4Wz050Qcj8z