Over 10 years of experience in FPGAs, processors, HDL development (Verilog) and system design. I have interests in high speed interfaces (PCIe, 10G/25G ethernet), algorithm implementation on FPGA and optimization.

Like to explore, study, teach, learn, share, design and debug.

Open to Collaboration:

I'm always interested in collaborating on FPGA design projects, exploring new technologies, and sharing knowledge within the FPGA community. Feel free to connect and reach out for discussions, collaborations, or assistance with FPGA-related challenges.

To contact me, drop an email to [email protected]