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Issues: Lampro-Mellon/LM-RISCV-DV

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15 Open 11 Closed
15 Open 11 Closed
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Issues list

Did you plan to used Force-riscv to generate random-instruction?
#101 opened Jan 8, 2022 by MasterJerryZh
Div/rem instruction handelling just before ecall invalid This doesn't seem right
#99 opened Mar 17, 2021 by saqibsaeed-lm
@saqibsaeed-lm
1
riscv-compliance misaligned and Zifencei tests failed
#97 opened Mar 10, 2021 by amnafayyaz28
Single tracer for Quasar enhancement New feature or request
#90 opened Feb 17, 2021 by saqibsaeed-lm
@saqibsaeed-lm
Quasar integration into lm-riscv-dv
#89 opened Feb 8, 2021 by mmhus
@saqibsaeed-lm
7
Integration of Ibtida Core in LM-RISC-V-DV Environment
#88 opened Jan 29, 2021 by haroon-shafique
@najeebafzal-rs
1
Add support for different configurations which comes with SweRV enhancement New feature or request
#86 opened Jan 21, 2021 by haroon-shafique
Add a generic cpp testbench for all the E-cores enabling verilator in the lm-riscv-dv environment
#85 opened Jan 21, 2021 by amnafayyaz28
Generate more interest in this repo help wanted Extra attention is needed
#84 opened Jan 20, 2021 by mmhus
Add torture to the flow enhancement New feature or request
#82 opened Jan 20, 2021 by mmhus
@amnafayyaz28
2
Add linting support using Github Actions enhancement New feature or request
#76 opened Jan 11, 2021 by haroon-shafique
Extend Tracer for RV32A enhancement New feature or request
#75 opened Jan 11, 2021 by najeebafzal-rs
Generate customized tests enhancement New feature or request
#74 opened Jan 11, 2021 by najeebafzal-rs
Add UVM based Testbench for Core Verification enhancement New feature or request
#71 opened Jan 7, 2021 by haroon-shafique
Add support for Python based flow of riscv-dv for generation of random assembly tests enhancement New feature or request
#70 opened Jan 7, 2021 by haroon-shafique
@amnafayyaz28
4
ProTip! Exclude everything labeled bug with -label:bug.