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1. Physical-Design Physical-Design Public

   Physical Design Flow from RTL to GDS using Opensource tools.

   70 13

2. spider-tronix/VLSI spider-tronix/VLSI Public archive

   RISC V core implementation using Verilog.

   Verilog 23 4

3. FPU-IEEE-754 FPU-IEEE-754 Public

   Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for float…

   Verilog 34 8

4. SpiderNitt/bee-bots SpiderNitt/bee-bots Public

   Developing a multi-bot system to build 2-d structures using innovative pick place and blockchain

   C 2 8

5. MYTH-RV32I-core-akilm MYTH-RV32I-core-akilm Public

   RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

   C 7 4

6. Logic-Gates-Sizing-Automation Logic-Gates-Sizing-Automation Public

   Determining the sizing of transistors using heuristic algorithms and logical effort to obtain optimal delay and power

   MATLAB 3