Skip to content

Issues: chipsalliance/chisel

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
38 Open 84 Closed
38 Open 84 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Chisel chokes on using elements of an unbound Aggregate as elements of a Record
#4215 opened Jun 24, 2024 by jackkoenig
2
Incorrect direction for mixed specified and unspecified directionality
#4204 opened Jun 21, 2024 by jackkoenig
1
It would be nice if ProbeValues of Literals would automatically expand widths
#4174 opened Jun 13, 2024 by jackkoenig
Probes should print more information about why types are non-equivalent
#4173 opened Jun 13, 2024 by jackkoenig
Source line + carat for errors should work for Scala CLI Example
#4172 opened Jun 13, 2024 by jackkoenig
Calling .asUInt on a Bool returns the Bool itself (rather than a true UInt)
#4163 opened Jun 11, 2024 by jackkoenig
1
Calling .pad on Bool results in requirement failure with no explanation
#4162 opened Jun 11, 2024 by jackkoenig
1
Connectable does not properly handle Views
#4024 opened Apr 23, 2024 by jackkoenig
Bad error message when calling .pad on a Bool bug
#3365 opened Jun 16, 2023 by jackkoenig
Bad error message from unsanitary port names
#2918 opened Jan 3, 2023 by jackkoenig
1
Chisel sometimes emits bulk connects when it should blast the connection apart
#2858 opened Nov 22, 2022 by jackkoenig
Reversing order of arguments to bit extraction gives terrible error message
#2762 opened Oct 5, 2022 by jackkoenig
1
Better Error Messages For Binary Incompatible Linking
#2625 opened Jul 11, 2022 by jackkoenig
Reflective naming will override the name given by naming plugin bug
#2554 opened Jun 1, 2022 by jackkoenig
1
Add Bundle.Init (analogous to VecInit / Bundle.Lit) good first issue An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#2435 opened Mar 7, 2022 by jackkoenig
6
Chisel 3.5.1 incorrectly warns on some Bundle traits bug
#2403 opened Feb 8, 2022 by jackkoenig
Objects extending Bundle give incorrect error messages
#2378 opened Feb 1, 2022 by jackkoenig
RegInit errors when passed a Bundle Literal bug
#1787 opened Feb 18, 2021 by jackkoenig 3.4.x
3
Name sanitation behavior changed between Chisel v3.3 and v3.4
#1784 opened Feb 10, 2021 by jackkoenig 3.5.0
3
Bad Error when calling .asUInt on empty Bundle bug
#1642 opened Oct 27, 2020 by jackkoenig
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2 bug
#1592 opened Sep 18, 2020 by jackkoenig
Add CONTRIBUTING.md
#1559 opened Aug 20, 2020 by jackkoenig
Printable should adopt a f"-like handling of %
#1522 opened Jul 25, 2020 by jackkoenig
Support $ in port names bug
#1391 opened Mar 28, 2020 by jackkoenig 3.3.x
Lazy val ports material ports in parent of modules where the lazy val is defined
#1328 opened Feb 10, 2020 by jackkoenig 3.3.x
1
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.