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Pull requests: chipsalliance/yosys-f4pga-plugins
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systemverilog-plugin: fix convert_range function
#533
by kamilrakoczy
was closed Oct 15, 2023
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systemverilog plugin: changes required for newer Surelog version
#531
by kamilrakoczy
was merged Aug 8, 2023
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yosys-systemverilog: fix multirange with dot usage
#529
by kamilrakoczy
was merged Jun 7, 2023
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systemverilog-plugin: fix anonymous enum when declared in submodules
#523
by kamilrakoczy
was merged Jun 6, 2023
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systemverilog-plugin: allow multirange access in dot access
#520
by wsipak
was merged May 31, 2023
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systemverilog-plugin: fix parsing unsized unbased consts
#519
by kamilrakoczy
was merged May 18, 2023
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systemverilog-plugin: split line and column in uhdmast_assert_log
#518
by kamilrakoczy
was merged May 19, 2023
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systemverilog-plugin: fix unnamed packed array
#513
by kamilrakoczy
was merged May 16, 2023
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systemverilog-plugin: update remove module message
#512
by kamilrakoczy
was merged May 16, 2023
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do not get value size of a constant from its typespec
#510
by wsipak
was merged May 12, 2023
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