JiVe is a CPU core that implements the [RISC-V instruction set] (http://www.riscv.org/).

JiVe is free and open hardware licensed under the BSD license.

• Small (~860 LUTs + 2 x EBRs on an iCE40UP5K)
• 16-bit ALU (for registers operations, address computation and PC)
• Execute an instruction in ~20 cycles
• PC is stored in a special CSR (address 0x007)

This CPU is meant to be used in control applications that do not need important processing power.

You are reading it right now.

This is the top level of the JiVe CPU

The 16-bit ALU (ADD, SUB, AND, OR, XOR, SHIFT). The shifter is also the address register for the memory access.

Instruction decoder, it generates a 6-bit jump micro-address, a 4-bit ALU operation conrtol, the immediate value and latches the different fields from the instruction.

Memory containing the CPU registers (2 x 1024 bits), the micro-code ROM (2 x 1024 bits) and some CSRs (4 x 1024 bits)

Additional CSRs for the interrupt management (mie, mip, cycle, cycleh).

File containing the micro-code ROM content.

Boot ROM that waits for an S-Record file on the serial port, loads it to RAM @ 0x80000000 and executes it. (only used by Verilator testbench, real ROM is in the radiant folder).

Memory-mapped timer implementing time, timeh, timecmp and timecmph registers.

Simple Rx/Tx UART 8N1 at a fixed baudrate (19200).

Minimal system-on-a-chip required by the contest (~1600 LUTs).

iCE40UP5K EBR model for Verilator.

iCE40UP5K low frequency oscillator model for Verilator.

iCE40UP5K SPRAM model for Verilator.

Source code for the UART/S-Record bootloader

Memory initialization files for the boot ROM and the register file.

Lattice Radiant project for the iCE40UP5K-B-EVN board. It requires a PMOD USBUART on the PMOD connector for the UART communication.

Compile script for the Verilator testbench. It also updates the JiVe simulator under riscv-compliance/riscv-jivesim

Main loop of the Verilator testbench. Accepted "$value$plusargs" parameters : +usec= : specify a simulation time in micro seconds. +msec= : specify a simulation time in milli seconds. +srec= : specify a S-Record file name to load into SPRAM. +syms= : specify a symbols file name for signature range extraction. +trc= : specify the trace file name for the RISC-V ISS +vcd= : specify the VCD file name

Verilator testbench configuration file.

Clock generator object to handle multiple clocks with different frequencies under Verilator.

RISC-V ISS and tracing for the Verilator co-simulation.

RISC-V compliance tests, type "make" to run the RV32I ones for the JiVe soft CPU. (first generate the RISC-V simulator with verilator/compile.sh)

SRecord v1.64 tool (http://srecord.sourceforge.net/).

Zephyr 1.13.0 with the necessary changes for the iCE40UP5K-B-EVN board.