mahmoudabdelhadii

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am I testing this code or is it testing me?

Mahmoud Abdelhadi mahmoudabdelhadii

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am I testing this code or is it testing me?

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I am a new graduate from the University of British Columbia majoring in electrical and computer Engineering with a focus on software engineering

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Toronto, Ontario
https://mahmoud.abdelhadii.com

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FormAI Public

TypeScript Updated Jun 29, 2024
portfolio Public

TypeScript Updated Jun 27, 2024
Formula-One-Predictor Public

Jupyter Notebook Updated May 30, 2024
mahmoudabdelhadii Public

Updated May 15, 2024
Amazoom-Warehouse-Automation Public

C# Updated Apr 11, 2024
16-Bit-RISC-Machine-II Public

Verilog Updated Nov 2, 2023
ChampSim Public
Forked from ChampSim/ChampSim

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

C++ Apache License 2.0 Updated Oct 11, 2023
Cup_capacitor Public

Assembly Updated Feb 24, 2022
QuadCore-RC4-Decryption Public

SystemVerilog Updated Feb 24, 2022
Simple-IPod-II-Embedded-system-volume-indication Public

Verilog Updated Feb 24, 2022
Simple-IPod-I Public

Verilog Updated Feb 24, 2022
Shakespearean-Multithreaded-Word-Count-Unit-testing Public

C# Updated Feb 24, 2022
Dual-input-breadboard-oscilloscope Public

Assembly Updated Feb 24, 2022
Metal-Detector Public

C Updated Feb 24, 2022
24-hour-alarm Public

Assembly Updated Feb 24, 2022
SVM-Cross-Vaildation Public

Jupyter Notebook Updated Feb 24, 2022
Python-linear-logit-reg-models Public

HW 1 for ELEC400M

Jupyter Notebook Updated Feb 24, 2022
Oscilloscope-sim-Nios-II Public

VHDL Updated Feb 24, 2022
Multi-threaded-Merge-sort Public

C# Updated Nov 4, 2021
Car-Simulator Public

C# Updated Oct 1, 2021
FPGA-Voice-Communcation-simulation Public

VHDL Updated Jun 17, 2021
Talking-Calculator Public

CPEN311

Verilog Updated Apr 18, 2021
lab5 Public

SystemVerilog Updated Mar 31, 2021
Lab4 Public

SystemVerilog Updated Mar 19, 2021
16-bit-RISC-Machine-I Public

C Updated Nov 6, 2019
lab7 Public

Verilog Updated Oct 30, 2019
CPENLAB6_2 Public

Verilog Updated Oct 24, 2019
CPENLAB6 Public

Verilog Updated Oct 22, 2019
CPENLAB5 Public

Verilog Updated Oct 21, 2019