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snbk001/README.md

Hi there 👋, I am Sudhee

RTL Design learner

Skills: Verilog / SystemVerilog / Makefile / C

  • 🔭 I’m currently working on SystemVerilog for Design and Synthesis.
  • 🌱 I’m currently learning SystemVerilog for RTL
  • 👯 I’m looking to collaborate on ASIC/FPGA/SOC Design.
  • 💬 Ask me about Verilog, SystemVerilog
  • 📫 How to reach me: snbkademane01@gmail.com
  • 😄 Pronouns: He/Him

Popular repositories Loading

  1. Verilog-Design-Examples Verilog-Design-Examples Public

    Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

    Verilog 72 13

  2. 100DaysofRTL 100DaysofRTL Public

    100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edg…

    SystemVerilog 25 3

  3. LIN-protocol LIN-protocol Public

    LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

    SystemVerilog 5

  4. 7T_SRAM 7T_SRAM Public

    7T SRAM Design submitted as a final report for Cloud Based Analog IC Design Hackathon conducted by IITH, Synopsis and VSD

  5. snbk001 snbk001 Public

    Config files for my GitHub profile.