Add emulator_ram section

timvideos · Jan 30, 2020 · 1e8165e · 1e8165e
1 parent 67d6798
commit 1e8165e
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/targets/waxwing/net.py b/targets/waxwing/net.py
@@ -22,6 +22,8 @@
 from liteeth.phy.mii import LiteEthPHYMII
 from liteeth.mac import LiteEthMAC
 
+from litex.soc.interconnect import wishbone
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -192,6 +194,10 @@ def __init__(self, platform, clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
+    mem_map = {
+        "emulator_ram": 0x50000000,  # (default shadow @0xd0000000)
+    }
+    mem_map.update(SoCSDRAM.mem_map)
 
     def __init__(self, platform, **kwargs):
         if 'integrated_rom_size' not in kwargs:
@@ -204,6 +210,11 @@ def __init__(self, platform, **kwargs):
 
         self.submodules.crg = _CRG(platform, clk_freq)
 
+        if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
+            size = 0x4000
+            self.submodules.emulator_ram = wishbone.SRAM(size)
+            self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size)
+
         # sdram
         if not self.integrated_main_ram_size:        
             sdram_module = MT46H32M16(clk_freq, "1:2")