OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
Jul 19, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
An abstraction library for interfacing EDA tools
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
SystemVerilog to Verilog conversion
Plugins for Yosys developed as part of the F4PGA project.
FPGA tool performance profiling
Sphinx Extension which generates various types of diagrams from Verilog code.
RealtimeIO for LinuxCNC based on an FPGA
Examples for the Lushay Labs tang nano 9k series
Physical Design Flow from RTL to GDS using Opensource tools.
XCrypto: a cryptographic ISE for RISC-V
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