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Issues: verilog-to-routing/vtr-verilog-to-routing
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Relax when router lookahead issues warnings for failure to find sample locations
#2636
opened Jun 30, 2024 by
petergrossmann21
Missing documentaion for some 3D-related tags and fields in the architecture reference
#2628
opened Jun 24, 2024 by
soheilshahrouz
See if simplifying the placement cost function slightly would speed up placement.
#2614
opened Jun 13, 2024 by
vaughnbetz
Loosen the minimum channel width and related metric pass characteristics for small circuits
#2613
opened Jun 13, 2024 by
vaughnbetz
Update documentation (and code if needed) to make placement constraints 3D
#2587
opened Jun 5, 2024 by
vaughnbetz
Remove Uses of std::iterator from VTR Libraries
#2557
opened May 24, 2024 by
AlexandreSinger
7 of 8 tasks
Giant distance from initial placing and routing solution to a better one VTR could have found.
#2544
opened Apr 25, 2024 by
WindFrank
3d switch block code, architecture files & reg tests
#2534
opened Apr 11, 2024 by
vaughnbetz
5 tasks
Parmys fails to properly handle multipliers with unequal input widths
#2532
opened Apr 11, 2024 by
WhiteNinjaZ
Add wire length attribute to RR graph output XML when using "--write_rr_graph" option
#2503
opened Mar 14, 2024 by
StephenMoreOSU
Designs with many different wire types fail at certain channel widths with an arithmetic exception
#2497
opened Mar 5, 2024 by
WhiteNinjaZ
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