Transfer between bus and register in 6502 CPU

Question

For one register of 6502 CPU (here X Index register) :

If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens ?

1. X Index register take the bus value
2. Bus value take the X Index register
3. Undefined and these signals should never be asserted at the same time
4. Other ?

I imagine that when a load signal occurs on a register, another register must have its bus enable signal to rely them together but what happens in this case ?

Answer 1

If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens?

You mean beside the fact, that it would need a useful instruction based on that function?

Since read and write port are different, X would be loaded with itself. A quick look at the Visual6502 graphics seem to support that.