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In a comment on https://retrocomputing.stackexchange.com/a/30215/4274 supercat made this interesting remark:

I think the critical paths with regard to cycle rate occurred while doing BCD math. A given 6502 which wasn't going to be used for BCD could probably run reliably at a faster rate than one which would be required to process BCD computations, but 1.79Mhz isn't really all that fast for a 6502 so I doubt there were any real timing constraints.

I think that's worth further investigation.

Is there any documentation or other evidence to show that BCD support was indeed the limiting factor on the 6502 clock speed in the 70s and early 80s, i.e. that it was sometimes what made the difference between a particular 6502 being able to run at 2 MHz or not?

If so, could you increase the clock speed just by deciding not to use BCD in your application? Or would you need to redesign the ALU to streamline the logic?

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    If there's any truth to this (and that is not to throw any shade at all on supercat believe me!) it's got to be down to a matter of gate delays in the ALU. And it that's the case then avoiding the BCD instructions would change nothing, you'd need a different ALU.
    – davidbak
    Commented Jun 29 at 17:22
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    We have a full netlist for the 6502, and it's already reverse engineered, so you can just sit down, identify the transistors used for BCD adjustment, remove them and recalculate the delay. Educated guess: It might get a tiny bit faster, but not much.
    – dirkt
    Commented Jun 29 at 18:31
  • 1.79Mhz.... Isn't that the same CPU clock as the NES? I heard somewhere that the BCD functionality on the 2A03 was disabled so Nintendo could skirt around patent laws.
    – qwerty keyboard
    Commented yesterday

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TL;DR: Yes, but No

  • Yes,
    • the BCD correction circuit is part of the default data path between ALU and A-register and
    • it does need some time to perform.
  • No, it's not relevant as for one
    • the correction circuit needs only a few nano seconds, but more important
    • the circuit is only active during PHI1.

PHI1 active is the internal cycle, while PHI2 is when memory gets accessed (*1) - and memory access is where the timing bottle neck of 6502 systems resides. A 1 MHz 6502 already needs 2 MHz memory (450 ns access time or better). The internal phase (PHI1) is extreme relaxed.

Is there any documentation or other evidence to show that BCD support was indeed the limiting factor on the 6502 clock speed in the 70s and early 80s,

Not that I ever heard of - even more as it's structure and circuitry is quite openly documented.

i.e. that it was sometimes what made the difference between a particular 6502 being able to run at 2 MHz or not?

You're aware that the 6502 existed in different speed grades?

  • 6502 for 1 MHz
  • 6502A for 2 MHz
  • 6502B for 3 MHz
  • 6502C for 4 MHz (*2)

As usual they are selected variant (early on) or simply marking. For all of them the relevant timing path is memory access.

If so, could you increase the clock speed just by deciding not to use BCD in your application?

No. Not unless one varies the clock source according to instruction use. As explained BCD correction is used during PHI1, where there is plenty time to spend a few nano seconds. The tight path is PHI2, where memory access is done (*3).

Or would you need to redesign the ALU to streamline the logic?

The 6502's circuitry is already quite optimized according to Ken Shirriff compact description (scroll down to "Comparison to the 6502").

*1 - The 6502 works essentially double clocked with alternating cycles used for internal operation and memory access. This is handled by creating two non overlapping clocks, one for each cycle, providing 4 flanks for operation.

*2 - 6502C, not 65C02. It's still a NMOS CPU.

*3 - Then again, this can already be done without looking at instructions. PHI2 depends on memory speed, while PHI1 on more relaxed internal operation speed. It was a known hack to operate a 6502 on a 3:5 clock, so 1.25 MHz for a 1 MHz CPU. This also shows why it wasn't used much: no real gain, but a much more complex clock circuit - for a CPU where one of it's major advantages was to not needing external clock circuitry.

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  • Although some systems don't start memory accesses until phi2, there are many that start memory accesses as soon as an address appears. Do you know of any timing analyses that would list the "actual" minimum high and low times, or for variants with separate phi1 and phi2 inputs, would given the mininum length of each quarter cycle?
    – supercat
    Commented Jun 29 at 20:04
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    If Φ1 is so relaxed, then can we run a 6502 faster by changing the clock's duty cycle or something? Say, if we use a 90% duty cycle, then at 1.8MHz the CPU would still only require around 450ns response time from the RAM, the same as a 1MHz clock at 50%.
    – Omar and Lorraine
    Commented yesterday
  • @OmarandLorraine That's exactly what footnote 3 is about. Of course this is only possible in systems not using the other half (like for video). And it violates official spec. You're example would run nice with today's WDC65C02. Back then it would have needed a 4 MHz 6502C at 1.6 MHz - all within spec.Likewise a 1:1 10 MHz clock would need expensive <50 ns RAM, running 10 MHz at 1:2 stretches that to 70 ns, allowing way more affordable RAM. all within (modern) spec.
    – Raffzahn
    Commented yesterday

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