How many lanes of PCIe does Thunderbolt 4 use?

Question

Searching shows that Thunderbolt 4 uses 4 lanes of PCIe 3.0; each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock. The pinout of Thunderbolt 4 is next:

The first question is why there are 4 lanes and not 2 if A2-A3 create a TX twisted pair and B10-B11 create an RX twisted pair, which together create 1 lane. Same idea for A10-A11, B2-B3. In such a way, it should be 2 lanes and not 4, but I have to miss something.

And second question: what pins are used for reference clock or in thunderbolt reference clock is not used at all?

Answer 1

Thunderbolt controller chips multiplex 4-lane PCIe and DisplayPort interfaces by tunneling them over the Thunderbolt interface.

So the lanes of Type-C connector do not carry PCIe protocol or DP protocol but Thunderbolt protocol which simply encapsulates the data with tags to signal where the data came from and where it should be sent out on the other end.

It uses two uplink lanes and two downlink lanes.

Just like DisplayPort, ThunderBolt does not send an explicit clock, but they use fixed link rate and the data stream is encoded with 8b10b (TB1&2) or 64b66b (TB3) line code which does not need a clock as it can be recovered at the receiving end.

Answer 2

While thunderbolt can carry PCIe traffic, it is not the same thing as PCIe. You can't connect a thunderbolt host directly to a PCIe peripheral or vice-versa.

Also while PCIe is normally operated with a shared reference clock, it doesn't actually require one. It is possible to operate transmitter and receiver with independent reference clocks and the specification makes allowances for the slight differences in data rates this can cause.

I would assume thunderbolt does something similar.

Answer 3

Thunderbolt 4 uses 4 lanes of PCIe 3.0

I'll admit this is a little confusing... in this case, "4 lanes of PCIe 3.0" is an indication of bandwidth, with no real association to the physical implementation... each Thunderbolt 4 lane being that much faster than PCIe.

Wikipedia does a good job of summarising this in the Thunderbolt 3 section:

It allows up to 4 lanes of PCI Express 3.0 (32.4 Gbit/s) for general-purpose data transfer, and 4 lanes of DisplayPort 1.4 HBR3 (32.40 Gbit/s before 8/10 encoding removal, and 25.92 Gbit/s after) for video,[78] but the maximum combined data rate cannot exceed 40 Gbit/s

... to clarify, the bandwidth is shared between PCIe and DisplayPort, with some flexibility on how much bandwidth is allocated to each interface - with a hard cap at 40 Gbit/s.

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each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock

This isn't true - for PCIe, the reference clock is not per-lane, it's for the whole link. As already noted, it's also possible to omit the clock, with the two endpoints having entirely independent reference clocks. A "PCIe lane" is two pairs (Tx and Rx). The reference clock is just to help the endpoints with natural drift that occurs with two independent clocks - it's not used to clock data directly.

With other protocols (including Thunderbolt), the clock can be "recovered" due to the line encoding that is used... fundamentally X-bit words are encoded into Y-bit symbols on the wire (where X < Y), and this encoding ensures there is a transition or edge regularly enough that the clock can be inferred from the signal.

Answer 4

Thunderbolt carries PCIe data packets but it is not electrically PCIe so there are zero PCIe lanes inside of a thunderbolt cable.

Some Thunderbolt controllers connect to 4 lanes of PCIe 3.0. This is probably what you read about, although other thunderbolt controllers do not connect to PCIe at all.