Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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PCIe digest explanation
In the PCIe standard they wrote the TLP messages may have digest section.
What is the digest of a TLP message described in the PCIe standard?
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PCIe implementation
I was reading about the PCIe stadard, it was mentioned about PCIe PHY, Switched, RootComplex and Bridges that make the PCIe fabric.
I'm trying to connect the dots between the physical hardware and the ...
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CPU to Switch SGMII port with PCIE 2.5Gb
I can't seem to find a 2.5 Gbps Ethernet controller that could be a bridge between the SGMII+ port and PCIe.
this is what I want to do:
I don't want to use PHY (from the copper 2.5G to 2.5G SGMII)
...
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PCIe Switch Doesn't Detect U.2 NVMe [migrated]
I am trying to get a U.2 NVMe (FIPS 140-2), Gen 2 (1x4) to get detected by our CPU conga-MA7 (COME 3.0 Type10 form factor). In between I have a PCIe Switch (PEX8718-AB80BI G). I am only using 2 lanes ...
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Origin and underlying sense of the term "Posted" in PCIe
When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...
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How many lanes of PCIe does Thunderbolt 4 use?
Searching shows that Thunderbolt 4 uses 4 lanes of PCIe 3.0; each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock. The pinout of Thunderbolt 4 is ...
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Designing a U.2 to M.2 NVMe adapter
I'm considering designing my own U.2 to M.2 converter card to make use of the four U.2 (PCIe 3.0 x4) connectors on my motherboard. Commercial products are available for doing this type of conversion, ...
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Why can't software capture PCIE packets?
I found this question in Stackoverflow and the answers say:
I don't believe so -- from a software viewpoint, PCI-E is quite well
disguised to look like (fast) PCI.
As far as I know, nearly the only ...
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What is the effect of disabling the scrambling on PCIe link stability?
In PCIe base specification document, it is mentioned that
Disabling scrambling is intended to help simplify test and debug equipment...
I am implementing my own custom gen2 PCIe IP in Verilog and I ...
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Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices
AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide.
In this AR, the author mentioned several components, namely:
PCIe PHY
GT QUAD
...
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PCIe hotplug hardware schematics reference design
I was going through this link, this was very wonderful
Does PCIe hotplug actually work in practice?
Following the above link, I had a question below:
I am looking for a "PCIe hotplug hardware ...
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Can a PCIe Bridge connect to multiple downstream devices using different functions?
My understanding of PCIe bridges is as follows:
A PCIe bridge appears as 1 device on the upstream bus, creates a new bus downstream of it, and whatever connects to the downstream side will appear as ...
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Can someone explain to me why the math for PCIe bandwidth doesn't add up?
Since PCIe g1 x1 is based off PCI 32/66 bandwidth of 2133.33 Mb (...
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PCIe connector overhang
There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
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Do extra PCIe lanes improve latency?
If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster.
But if you never need ...
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