All Questions
33
questions
-1
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0
answers
29
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Feeding data stream to FPGA using PCIe [closed]
I am trying to use PCIe with ultrascale+ device and feed the fpga with data stream and send it to another device using PCIe over SFP+ optical cable. However, I don't know how to feed data to the fpga (...
0
votes
2
answers
193
views
Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices
AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide.
In this AR, the author mentioned several components, namely:
PCIe PHY
GT QUAD
...
- 465
2
votes
0
answers
361
views
Studying the PCIe/CXL/CCIX internals at home
Could anybody recommend me a good starting point for self-studying the PCIe internals?
I imagine some kind of an FPGA-based course, covering PCIe endpoint, root complex and switching functionalities. ...
- 21
1
vote
1
answer
372
views
FPGA-based SSD host controller without transceivers
Problem: I am looking for options to design a host controller for SSD (SATA or nVME) using transceiver-less FPGA.
Question: What are the current state-of-the-art practices of doing such designs?
My ...
- 412
2
votes
1
answer
743
views
What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.
A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
- 579
2
votes
2
answers
760
views
Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?
The Intel Cyclone IV FPGA supports PCI Express (PCIe) generation 1, and the IO standard for the Tx output is PCML at 1.5 V.
The Cyclone IV Device Handbook volume 2 page 1-13 describes that the Tx ...
- 579
1
vote
0
answers
162
views
Selecting FPGA to implement PCIe
Hy i would like to play around with PCIe.
My Goals are:
Implement a read and write able BAR.
Implement a DMA that copies data from my Device to the PCs Memory.
I am beginer Level at FPGAs I have a ...
- 111
0
votes
1
answer
563
views
What is the purpose of EEPROM in the PCIe accelerator card?
As i am exploring the many PCIe accelerator card features and design aspects, in few design I could find the Block called as 'MAC ID PROM'. And in the design they have provided the EEPROM circuit.
In ...
- 47
1
vote
3
answers
388
views
Creating hardware acceleration card with PCIe implemented in an FPGA
PCIe offers a very high speed interface between a peripheral card and PC. Sending and receiving data from the FPGA side which contains the PCIe IP seems to make sense. However, I am confused how it ...
- 2,103
3
votes
2
answers
2k
views
Does PCIe 100ms boot-up time requirement including the entire FPGA device?
we know most of the FPGA vendor have way to ensure the entire FPGA device can be configured within the 100ms time. However, since most of the PCIe solution is a harden block (dedicated circuitry) ...
- 185
3
votes
1
answer
303
views
Can a non-enumerated device conduct DMA operations?
PCIe devices can read or write to memory, i.e. can do DMA without requiring a device driver. For example: pcileech (The PCIe FPGA device is controlled by another computer). If I remember correctly, if ...
- 33
0
votes
1
answer
134
views
PCI based system debuging
I've came across some products that help you troubleshoot a computer that won't POST, with listening and capturing traffic on PCI bus during system startup.
They essentially know the normal procedure,...
- 87
3
votes
1
answer
244
views
PCIe gen3 over a FMC connector
I am thinking to connect PCIe devices to my FPGA board via FMC connector (using a PCIe to FMC adapter).
Will I get full PCIe bandwidth for those devices on the FMC connector?
Not considering FPGA ...
- 135
2
votes
1
answer
1k
views
How to choose a right user interface in PCIe DMA subsystem (AXI Memory Map / AXI Streaming)
Looking at the PCIe DMA solution offered by different FPGA vendors, there are 2 main user-interface options:
1) AXI Memory Map (Altera use Avalon-MM)
2) AXI Streaming (Altera use Avalon-ST)
Using ...
- 185
0
votes
1
answer
199
views
Multi-channels DMA Subsystem for PCI Express
Say i have a PCIe Gen2 x4 link running in a DMA subsystem. May I know when do we need multi-channels DMA configuration? For example, FPGA vendor like Xilinx offer up to 4-read & 4-write data ...
- 185