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2 votes
1 answer
743 views

What value to use for Byte Count field in PCI Express (PCIe) IO read completion?

In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read. A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
EquipDev's user avatar
  • 579
2 votes
1 answer
221 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
Simon Richter's user avatar
2 votes
3 answers
2k views

PCI-Express and FPGA Development Boards [closed]

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
Sam's user avatar
  • 145
6 votes
2 answers
5k views

PCIe fails on "polling compliance" state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
Randomblue's user avatar
  • 11.1k
2 votes
1 answer
387 views

FPGA project sanity check, PCIE and video processeing

I have an Altera DE4 education FPGA that I'd like to use for video processing... But the thing doesn't have many ports to work with, and I don't have the funds to purchase any daughter boards. My ...
ZacAttack's user avatar
  • 135