All Questions
13
questions
0
votes
0
answers
37
views
PCIe connector overhang
There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
- 73
2
votes
1
answer
2k
views
PCIe Gen4: inter-pair skew: any limits?
For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either:
2 TX differential pairs (of different ...
- 7,697
2
votes
0
answers
43
views
Is compliance testing necessary for PCIE3.0 if the SOC and Wi-Fi chipset is on the same board?
In my product, PCIe is just used for data transmission between SOC and Wi-Fi chipset. It's not used for any other purpose. Is compliance testing necessary for this scenario?
What type of SI ...
- 29
3
votes
1
answer
339
views
Mini PCIe vs PCIe layout
I am designing fast digital lines for the first time.
I want to change the PCIe connector of the CM4 IO board to mini PCIe.
I reviewed the AN307: Hardware Design Considerations for PCI ExpressTM and ...
- 173
1
vote
1
answer
1k
views
PCIE Gen 2 Intra-Pair Skew
I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair:
Considering the capacitors the skew is ~50 mills:
this is the relevant part of the ...
- 1,067
1
vote
1
answer
641
views
Can I avoid blind vias in this PCI-E gold finger fanout?
I'm planning a PCB project with PCI-E connector. After looking at some docs about PCI-E, I found one problem regarding the fanout the PCI-E gold fingers, the X16 pinout defines as below (part of whole ...
- 5,886
0
votes
1
answer
927
views
Does anybody have PCIe (3.0) aka PCI Express module card edge connector technical drawing? [duplicate]
I was searching through the internet to find PCI Express card edge connector footprints / technical drawings / pin spacing / layout of the module cards that you stick in these connectors you can find ...
- 103
8
votes
1
answer
1k
views
USB 3.1 over PCIe board edge connector
I am designing a system with a carrier board that has all of active logic on one board and most connectors on a backplane board. The interface between the two boards is a x16 PCIe board edge connector....
- 101
2
votes
1
answer
3k
views
Lane Reversal on PLX PCIe Switches
I'm currently designing a carrier board on which is integrated a PLX PEX 8750 PCIe switch connected to several PCIe connectors.
The problem occurs when routing PCIe lanes, since I can't route them ...
- 45
21
votes
1
answer
5k
views
PCIe, diagnosing and improving an eye diagram
I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector).
The root ...
- 301
1
vote
2
answers
986
views
PCIe branching - Requirement of Switch
Considering the following scenario:
A designer wants to connect 3 devices on a PCIe x4 finger edge connector, commonly found on mother boards.
All 3 devices will be populated on the same PCIe card.
...
- 169
4
votes
3
answers
14k
views
AC coupling on PCIe layout
I'm working on a layout in which two chips connect to each other through a 1x PCIe bus. The two chips are on one board.
One of the chips is the Xilinx Spartan6 LX75T so I've been working with the ...
- 536
2
votes
3
answers
766
views
Guidelines on branching of a PCI express signal
We have 3 PCIe slots on a board, let's call them A, B and C. On this board, slot A will always be populated with a PCIe device, however, among slots B and C, only one of them will be populated.
There ...
- 2,260