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2 votes
1 answer
1k views

Performance difference when comparing PCIe DMA vs. MMIO for same data access size

Some PCIe devices can map their own device memory region fully to contiguous host physical memory address space through a feature called PCIe Resizable BAR (base address register), which makes it ...
hurryman2212's user avatar
1 vote
1 answer
146 views

Linking WiFi MCU to Ethernet PHY via PCIe

I'm trying to link this Ethernet PHY to this WiFi 6 MCU via PCIe to make a single port router. Can I directly connect these two, or do I need some kind of host CPU with two PCIe slots to link them? ...
cdubs's user avatar
  • 425
3 votes
1 answer
5k views

Minimum requirements to interact with PCI Express

I have a relatively simple project (from the user point of view) in mind. I want to develop a very simple PCI Express (x1) card that users can put into their system and toggle some GPIO's from a GUI ...
DEKKER's user avatar
  • 775
3 votes
1 answer
941 views

Understanding PCIE and FPGA clock "magic"

I've been trying to understand how PCIE clocking works when it comes to connecting an FPGA to a PCIE slot in a motherboard. Looking at page 12 of this schematic for exampe: https://www.xilinx.com/...
dem0's user avatar
  • 31
0 votes
1 answer
712 views

Connect PCIe x1 port to an ASIC PCIe x4 [closed]

I want to connect a microcontroller with a PCIe x1 port to an ASIC with PCIe x4 interface. It is not possible to connect microcontroller to lane 0 of ASIC, and it should be connected to other lanes (...
moji_fara's user avatar
1 vote
2 answers
773 views

PC shares memory with external microcontroller

I'm looking for a PC hardware interface that matches these needs- The PC will constantly be busy performing calculations. Each time there is a calculation result (every ~1ms) I want it to share it ...
Elad's user avatar
  • 21