All Questions
22
questions
7
votes
2
answers
959
views
PCIe implementation
I was reading about the PCIe stadard, it was mentioned about PCIe PHY, Switched, RootComplex and Bridges that make the PCIe fabric.
I'm trying to connect the dots between the physical hardware and the ...
- 95
0
votes
1
answer
33
views
Origin and underlying sense of the term "Posted" in PCIe
When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...
- 11
0
votes
2
answers
95
views
Do extra PCIe lanes improve latency?
If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster.
But if you never need ...
- 981
0
votes
2
answers
406
views
PCIe Domain, Bus, Device, Function limits
I am new to PCIe. I would like to understand 256 (bus), 32 (device), 8 (function). I am trying to visualise these PCIe slots on a motherboard. I am used to desktop motherboards where we have one ...
- 93
7
votes
3
answers
3k
views
How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
- 71
1
vote
0
answers
202
views
Remapping a PCI(e) device when another core is accessing the device
According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)?
If not, ...
- 157
0
votes
0
answers
182
views
Do PCI Express devices' interrupts always go through a PIC or an APIC?
My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC?
https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
- 93
0
votes
1
answer
333
views
PCIe PRST pin functionality at M.2 connector (B) with SATA device (reboot detection)
M.2 connector type (key B) support PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus.
I want to use SATA interface with my device, but I need to detect the reboot of the host ...
- 11
1
vote
1
answer
255
views
What limit the pci-e splitting on this case?
I am trying to understand the PCI-E principles but I miss something.
The reason why I need to understand that is because I working on a project that involve a lot of SATA HDD to be connected to one ...
- 11
8
votes
1
answer
2k
views
Backwards compatibility of PCIe AC coupling capacitors
The PCIe base spec mentions that platforms operating only at 2.5GT/s or 5GT/s may use AC coupling capacitors in the 75nF-265nF and that platforms supporting 8GT/s and above must use 176nF-265nF.
...
- 225
2
votes
1
answer
743
views
What value to use for Byte Count field in PCI Express (PCIe) IO read completion?
In PCI Express (PCIe) a completion packet is to be generated for both memory read and IO read.
A Byte Count field is part of the completion packet, and for a memory read (MRd) in the simple case, this ...
- 579
1
vote
0
answers
616
views
Does my PCIe platform support CLKREQ#?
I succeeded entering ASPM L1.1 and L1.2 for my device. After entering ASPM L1.1 or L1.2 and trying to initiate to exit from Host side, I saw some hosts that are:
• Able to initiate an exit from ASPM ...
- 11
1
vote
1
answer
1k
views
PCIE Gen 2 Intra-Pair Skew
I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair:
Considering the capacitors the skew is ~50 mills:
this is the relevant part of the ...
- 1,067
1
vote
0
answers
285
views
Unable to Identify VL805 device
I have designed a PCIE to USB3 converter device that is based to VIA LABS VL805 Q6 Chip.
My problem that I can't recognize the VL805 chip in Linux, using the command "lspci":
here is the ...
- 1,067
0
votes
1
answer
333
views
The detail of External PCIe cabling specification?
As searching on the Internet, I found that the PCI group has released the "PCIe External cabling specifications". But I can not download the document because I am not a member of the PCI ...
