- Bulacan, Philippines
- https://www.linkedin.com/in/angelo-jacobo
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UberDDR3 Public
Opensource DDR3 Controller
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Hamming-ECC Public
Forked from RoaLogic/Hamming-ECCHamming ECC Encoder and Decoder to protect memories
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RISC-V Public
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
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eth10g Public
Forked from ZipCPU/eth10g10Gb Ethernet Switch
C Apache License 2.0 UpdatedJul 19, 2023 -
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DDR Public
Forked from buttercutter/DDRA simple DDR3 memory controller
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ddr3-controller Public
Forked from someone755/ddr3-controllerA DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
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Customize-Android-Apps Public
This contains my notes on how to customize existing Android apps such as changing app name, app icon, hiding app from the app drawer, and others.
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Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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SDCard_Driver_Test Public
Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.
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icestudio-examples Public
Forked from intergalaktik/icestudio-examples❄️ Icestudio examples - Community contributions
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Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
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ULX3S_FPGA_Camera_Streaming Public
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
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FPGA_OV7670_Camera_Interface Public
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
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Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
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Python_Scripts Public
Just a collection of my python scripts
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FPGA_Asynchronous_FIFO Public
FIFO implementation with different clock domains for read and write.
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FPGA_SDRAM_Controller Public
SDRAM controller optimized to a memory bandwidth of 316MB/s
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FPGA_I2C_Implementation Public
Bit-bang i2c protocol for interfacing with DS1307 RTC
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FPGA_Book_Experiments Public
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
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vsdstdcelldesign Public
Forked from nickson-jose/vsdstdcelldesignThis repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an…
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zipstormmx Public
Forked from ZipCPU/zipstormmxZipSTORM-MX, an iCE40 ZipCPU demonstration project
Verilog UpdatedAug 19, 2019