Verilator open-source SystemVerilog simulator and lint system

XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4

Instruction set simulator for RISC-V, MIPS and ARM-v6m

RISC-V CPU Core (RV32IM)

SDRAM controller with AXI4 interface

FX68K 68000 cycle accurate SystemVerilog core

Genesis-Plus-GX based MEGADRIVE/GENESIS emulator for the Maixduino

VHDL compiler and simulator

Yosys Open SYnthesis Suite

Mirror of tachyon-da cvc Verilog simulator

Primary GIT Repository for the Zephyr Project

Dockerfile for OSS CVC verilog simulator

c++ Bjarne Stroustrup