Merge pull request #238 from antmicro/netv2

Add NeTV2 support and HDMI2PCIe

.travis.yml

@@ -82,6 +82,7 @@ env:
    - C=mor1kx           TC="ise"       P=opsis             T="base net"
    - C=mor1kx           TC="ise"       P=pipistrello       T="base"
    # VexRISCV
+   - C=vexriscv         TC="vivado"    P=netv2             T="base net"
    - C=vexriscv         TC="vivado"    P=arty              T="base net"
    - C=vexriscv         TC="vivado"    P=mimas_a7          T="base net"
    - C=vexriscv         TC="ise"       P=mimasv2           T="base"
@@ -117,6 +118,10 @@ env:
    - C=lm32             TC="ise"       P=atlys             T="hdmi2usb"
    - C=lm32             TC="ise"       P=opsis             T="hdmi2usb"
    #--------------------------------------------
+   # HDMI2USB Targets
+   #--------------------------------------------
+   - C=vexriscv         TC="vivado"    P=netv2             T="hdmi2pcie"
+   #--------------------------------------------
    # MicroPython Targets
    #--------------------------------------------
    # FIXME: Add some here

firmware/Makefile

@@ -45,6 +45,7 @@ OBJECTS=\
 	tofe_eeprom.o \
 	uptime.o \
 	version.o \
+	pcie.o \
 	$(FIRMBUILD_DIRECTORY)/version_data.o \
 	$(FIRMBUILD_DIRECTORY)/hdmi_in1.o \
 	boot-helper-$(CPU).o

firmware/ci.c

@@ -647,6 +647,10 @@ static void video_matrix_list(void)
 #ifdef CSR_HDMI_IN1_BASE
 	wprintf("input1 (1): %s\n", HDMI_IN1_MNEMONIC);
 	wputs(HDMI_IN1_DESCRIPTION);
+#endif
+#ifdef CSR_PCIE_PHY_BASE
+	wprintf("pcie (x):\n");
+	wprintf("  PCIe buffer\n");
 #endif
 	wprintf("pattern (p):\n");
 	wprintf("  Video pattern\n");
@@ -669,7 +673,7 @@ static void video_matrix_list(void)
 
 static void video_matrix_connect(int source, int sink)
 {
-	if(source >= 0 && source <= VIDEO_IN_PATTERN)
+	if(source >= 0 && source < VIDEO_IN_MAX)
 	{
 		if(sink >= 0 && sink <= VIDEO_OUT_HDMI_OUT1) {
 			wprintf("Connecting %s to output%d\n", processor_get_source_name(source), sink);
@@ -693,6 +697,12 @@ static void video_matrix_connect(int source, int sink)
 			processor_set_encoder_source(source);
 			processor_update();
 		}
+#endif
+#ifdef CSR_PCIE_PHY_BASE
+		else if(sink == VIDEO_OUT_PCIE) {
+			wprintf("Connecting %s to PCIe\n", processor_get_source_name(source));
+			processor_update();
+		}
 #endif
 	}
 }
@@ -1097,6 +1107,9 @@ void ci_service(void)
 			else if((strcmp(token, "pattern") == 0) || (strcmp(token, "p") == 0)) {
 				source = VIDEO_IN_PATTERN;
 			}
+			else if((strcmp(token, "pcie") == 0) || (strcmp(token, "x") == 0)){
+				source = VIDEO_IN_PCIE;
+			}
 			else {
 				wprintf("Unknown video source: '%s'\n", token);
 			}
@@ -1113,6 +1126,9 @@ void ci_service(void)
 			else if((strcmp(token, "encoder") == 0) || (strcmp(token, "e") == 0)) {
 				sink = VIDEO_OUT_ENCODER;
 			}
+			else if((strcmp(token, "pcie") == 0) || (strcmp(token, "x") == 0)) {
+				sink = VIDEO_OUT_PCIE;
+			}
 			else
 				wprintf("Unknown video sink: '%s'\n", token);
 

firmware/framebuffer.h

@@ -22,16 +22,17 @@
  * Frame buffers must be aligned to XXX boundary.
  *
  *  0x01000000 - Pattern Buffer - Frame Buffer n
+ *  0x02000000 - PCIe Buffer - Frame Buffer n
  *
  * Each input then has 3 frame buffers spaced like this;
  *  // HDMI Input 0
- *  0x02000000 - HDMI Input 0 - Frame Buffer n
- *  0x02040000 - HDMI Input 0 - Frame Buffer n+1
- *  0x02080000 - HDMI Input 0 - Frame Buffer n+2
+ *  0x03000000 - HDMI Input 0 - Frame Buffer n
+ *  0x03040000 - HDMI Input 0 - Frame Buffer n+1
+ *  0x03080000 - HDMI Input 0 - Frame Buffer n+2
  *  // HDMI Input 1
- *  0x03000000 - HDMI Input 1 - Frame Buffer n
- *  0x03040000 - HDMI Input 1 - Frame Buffer n+1
- *  0x03080000 - HDMI Input 1 - Frame Buffer n+2
+ *  0x04000000 - HDMI Input 1 - Frame Buffer n
+ *  0x04040000 - HDMI Input 1 - Frame Buffer n+1
+ *  0x04080000 - HDMI Input 1 - Frame Buffer n+2
  *  ...
  *  // HDMI Input x
  *  0x0.000000 - HDMI Input x - Frame Buffer n
@@ -41,14 +42,17 @@
  */
 #define FRAMEBUFFER_OFFSET		0x01000000
 #define FRAMEBUFFER_PATTERNS		1
+#define FRAMEBUFFER_PCIE_BUFFERS	1
 
 #define FRAMEBUFFER_PIXELS_X		1920	// pixels
 #define FRAMEBUFFER_PIXELS_Y		1080	// pixels
 #define FRAMEBUFFER_PIXELS_BYTES	2	// bytes
 
 #define FRAMEBUFFER_BASE(x)			((x+1)*FRAMEBUFFER_OFFSET)
 #define FRAMEBUFFER_BASE_PATTERN		FRAMEBUFFER_BASE(0)
-#define FRAMEBUFFER_BASE_HDMI_INPUT(x)		FRAMEBUFFER_BASE(x+FRAMEBUFFER_PATTERNS)
+#define FRAMEBUFFER_BASE_PCIE			FRAMEBUFFER_BASE(FRAMEBUFFER_PATTERNS)
+#define FRAMEBUFFER_BASE_HDMI_INPUT(x)		FRAMEBUFFER_BASE(x+FRAMEBUFFER_PATTERNS+FRAMEBUFFER_PCIE_BUFFERS)
+
 
 // Largest frame size at 16bpp (ish)
 #define FRAMEBUFFER_SIZE		0x400000 // bytes

firmware/pcie.c

@@ -0,0 +1,10 @@
+#include "pcie.h"
+#include "framebuffer.h"
+
+// Last 4 bytes of the buffer area
+volatile unsigned int * pcie_in_fb_index = (unsigned int*)(MAIN_RAM_BASE + FRAMEBUFFER_BASE_PCIE + 4 * FRAMEBUFFER_SIZE - sizeof(unsigned int));
+volatile unsigned int * pcie_out_fb_index = (unsigned int*)(MAIN_RAM_BASE + FRAMEBUFFER_BASE_PCIE + 8 * FRAMEBUFFER_SIZE - sizeof(unsigned int));
+
+unsigned int pcie_in_framebuffer_base(char n) {
+	return FRAMEBUFFER_BASE_PCIE + n * FRAMEBUFFER_SIZE;
+}

firmware/pcie.h

@@ -0,0 +1,8 @@
+#ifndef __PCIE_H
+#define __PCIE_H
+
+extern volatile unsigned int * pcie_out_fb_index;
+extern volatile unsigned int * pcie_in_fb_index;
+unsigned int pcie_in_framebuffer_base(char);
+
+#endif

firmware/processor.c

@@ -23,6 +23,8 @@
 #include <generated/mem.h>
 #include <hw/flags.h>
 #include <time.h>
+#include <system.h>
+#include <time.h>
 
 #include "hdmi_in0.h"
 #include "hdmi_in1.h"
@@ -33,6 +35,7 @@
 #include "mmcm.h"
 #include "processor.h"
 #include "heartbeat.h"
+#include "pcie.h"
 
 /*
  ----------------->>> Time ----------->>>
@@ -705,13 +708,18 @@ char * processor_get_source_name(int source) {
 	memset(processor_buffer, 0, 16);
 	if(source == VIDEO_IN_PATTERN)
 		sprintf(processor_buffer, "pattern");
+	else if(source == VIDEO_IN_PCIE)
+		sprintf(processor_buffer, "pcie");
 	else
 		sprintf(processor_buffer, "input%d", source);
 	return processor_buffer;
 }
 
 void processor_update(void)
 {
+#ifdef CSR_PCIE_PHY_BASE
+	unsigned int pcie_in_fb_idx = (*pcie_in_fb_index) >> 24;
+#endif
 #ifdef CSR_HDMI_OUT0_BASE
 	/*  hdmi_out0 */
 #ifdef CSR_HDMI_IN0_BASE
@@ -721,9 +729,14 @@ void processor_update(void)
 #ifdef CSR_HDMI_IN1_BASE
 	if(processor_hdmi_out0_source == VIDEO_IN_HDMI_IN1)
 		hdmi_out0_core_initiator_base_write(hdmi_in1_framebuffer_base(hdmi_in1_fb_index));
+#endif
+#ifdef CSR_PCIE_PHY_BASE
+	if(processor_hdmi_out0_source == VIDEO_IN_PCIE)
+		hdmi_out0_core_initiator_base_write(pcie_in_framebuffer_base(pcie_in_fb_idx));
 #endif
 	if(processor_hdmi_out0_source == VIDEO_IN_PATTERN)
 		hdmi_out0_core_initiator_base_write(pattern_framebuffer_base());
+
 #endif
 
 #ifdef CSR_HDMI_OUT1_BASE
@@ -735,6 +748,10 @@ void processor_update(void)
 #ifdef CSR_HDMI_IN1_BASE
 	if(processor_hdmi_out1_source == VIDEO_IN_HDMI_IN1)
 		hdmi_out1_core_initiator_base_write(hdmi_in1_framebuffer_base(hdmi_in1_fb_index));
+#endif
+#ifdef CSR_PCIE_PHY_BASE
+	if(processor_hdmi_out0_source == VIDEO_IN_PCIE)
+		hdmi_out1_core_initiator_base_write(pcie_in_framebuffer_base(pcie_in_fb_idx));
 #endif
 	if(processor_hdmi_out1_source == VIDEO_IN_PATTERN)
 		hdmi_out1_core_initiator_base_write(pattern_framebuffer_base());
@@ -757,6 +774,11 @@ void processor_update(void)
 		encoder_reader_base_write(pattern_framebuffer_base());
 #endif
 
+#ifdef CSR_PCIE_PHY_BASE
+	/*  PCIe capture*/
+	/*  FIXME: add code here when PCIe output starts to use DMA */
+#endif
+
 #ifdef CSR_HDMI_IN0_BASE
 	hb_service(hdmi_in0_framebuffer_base(hdmi_in0_fb_index));
 #endif

firmware/processor.h

@@ -45,15 +45,18 @@ enum {
 };
 
 enum {
-	VIDEO_IN_HDMI_IN0=0,
+	VIDEO_IN_PATTERN=0,
+	VIDEO_IN_HDMI_IN0,
 	VIDEO_IN_HDMI_IN1,
-	VIDEO_IN_PATTERN
+	VIDEO_IN_PCIE,
+	VIDEO_IN_MAX
 };
 
 enum {
 	VIDEO_OUT_HDMI_OUT0=0,
 	VIDEO_OUT_HDMI_OUT1,
-	VIDEO_OUT_ENCODER
+	VIDEO_OUT_ENCODER,
+	VIDEO_OUT_PCIE
 };
 
 extern int processor_mode;

firmware/reboot.c

@@ -14,10 +14,17 @@
 
 extern void boot_helper(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int addr);
 
+#ifdef CSR_CTRL_BASE
+void reboot(void)
+{
+	ctrl_reset_write(1);
+}
+#else
 void reboot(void)
 {
 	boot(0, 0, 0, CONFIG_CPU_RESET_ADDR);
 }
+#endif
 
 void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int addr)
 {

make.py

@@ -153,11 +153,13 @@ def main():
         vns = platform.build(soc, build_dir=os.path.join(builddir, "gateware"))
 
     if hasattr(soc, 'pcie_phy'):
-        from targets.common import cpu_interface
-        csr_header = cpu_interface.get_csr_header(soc.get_csr_regions(), soc.get_constants())
+        from litex.soc.integration.export import get_csr_header, get_soc_header
+        csr_header = get_csr_header(soc.csr_regions, soc.constants, with_access_functions=False)
+        soc_header = get_soc_header(soc.constants, with_access_functions=False)
         kerneldir = os.path.join(builddir, "software", "pcie", "kernel")
         os.makedirs(kerneldir, exist_ok=True)
         write_to_file(os.path.join(kerneldir, "csr.h"), csr_header)
+        write_to_file(os.path.join(kerneldir, "soc.h"), soc_header)
 
     if hasattr(soc, 'do_exit'):
         soc.do_exit(vns, filename="{}/analyzer.csv".format(testdir))