Mark Bellows

Salt Lake City, Utah, United States Contact Info
780 followers 500+ connections

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About

RESULTS-DRIVEN COMPUTER HARDWARE ENGINEER FOR INCREASING QUALITY AND…

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Experience & Education

  • Idaho Scientific

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Volunteer Experience

  • Volunteer: Scoutmaster, Cubmaster, Committee Chair

    Boy Scouts of America

    - 26 years 4 months

    Children

    It is fulfilling to help mentor the future engineers, doctors and adults in a fun, outdoor environment. As a leader, you work with teaching the youth, the other leaders and parents about what it takes to have a strong character. Not only did I work at my pack or troop level, I have lead training and have been part of several training activities for adults.

Courses

  • Anal Geom & Calc 2

    MATH 113

  • C++ For C Programmers, Part A from Coursera

    University of California

  • Cadence SKILL Language Programming

    Cadence Course

  • ChipBench Placement

    IBM EDA

  • ChipBench Tcl

    IBM EDA

  • Computer Architecture

    -

  • Computer Organization & Design I

    -

  • Computer Organization & Design II

    -

  • Computer System Perfomance Analysis

    -

  • Data Communications, Networks

    -

  • Digital Signal Processing

    -

  • Effective Leadership: It's not just Positional

    RTTC Source

  • Intoduction to Einstimer

    IBM EDA

  • Intro Comp Prog

    C S 142

  • Intro to Elec Engr

    EL EN 100

  • Introduction to Object Oriented Programming in C++

    -

  • Introduction to Parallel Computing

    -

  • Management Perspective Seminars

    IBM

  • Mangement for Engineers

    -

  • Mastering SystemVerilog UVM, Sutherland HDL, July 2014

    -

  • Parallel Processing I

    -

  • Principles of Physics 1

    PHSCS 121

  • Project Management Fundamentals

    20210

  • Static Timing

    webct8943

  • Structure of High Level Languages

    -

  • SystemVerilog Object Oriented Verification, Sutherland HDL, June 2014

    -

  • Telecommunication Networks

    -

  • Tensillica ConnX B10 DSP v9.6

    -

  • UVM for Verification Part 1 : Fundamentals and Part 2 : Projects

    Udemy Business

  • VHDL Coding Styles for Synthesis

    SynthWorks Design Inc

  • VHDL Soup to Nuts

    IBM EDA

  • VHDL/VLSI Logic System Design

    ATWC0901

  • VLSI Design I

    -

  • VLSI Design II

    -

Projects

  • Consulting on Image Processing Unit

    -

    Provided engineering and technical pre-silicon services - writing and debugging C++ code, creating scripts in python/shell for working with the emulator environments. Found problems in stack overflows, assembly code, Learned about Tensilica Xtensa Processors. Learned Mercurial. Provided review and suggestions for silicon validation focus areas.

  • Intel Core Gen 14 Processor — Synthetic Validation Lead (North)

    -

    Intel Consumer processor validated with new content, validating 8 different IPs, developing novel testing methods. The North IPs are ones considered closest to the CPU and are generally more memory consuming. Also worked on stress testing with concurrent applications/stimulus. These IPs were graphics, display, media, camera, gaussian normal distribution, CPUs, Memory and the fabric between them.

  • Intel Low Power Gen 11 & Gen 9 Processors — Memory Validation

    -

    Intel Consumer and Devices Processors - verifying memory controllers and subsystems. Created checkers for proper configuration, debugging, triaging and checking against specifications. Including customer support on their site.

  • IBM i/p/zSeries PowerPC A25, RS64-II, III, IV

    -

    Various projects and subsystems - cache controller validation-verification, memory controller design, network processor design, floating point unit verification

Honors & Awards

  • Patents - List from PTO

    US/GB/CH

    62 US Patents Granted
    5 SIMD execution
    o 4 Network Processor
    o 53 Memory Controller

    Sample List

    Title: MULTIPLE PROCESSOR DELAYED EXECUTION
    02/19/2014 Issued as Patent 2500081 in GB

    Title: MEMORY COMMAND AND ADDRESS CONVERSION BETWEEN AN XDR INTERFACE AND A DOUBLE DATA RATE INTERFACE
    07/13/2010 Issued as Patent 7757040 in US

    Title: SYNAPSE: RANK SELECT OPERATION BETWEEN AN XIO INTERFACE AND A DOUBLE DATA RATE INTERFACE
    11/23/2010 Issued as…

    62 US Patents Granted
    5 SIMD execution
    o 4 Network Processor
    o 53 Memory Controller

    Sample List

    Title: MULTIPLE PROCESSOR DELAYED EXECUTION
    02/19/2014 Issued as Patent 2500081 in GB

    Title: MEMORY COMMAND AND ADDRESS CONVERSION BETWEEN AN XDR INTERFACE AND A DOUBLE DATA RATE INTERFACE
    07/13/2010 Issued as Patent 7757040 in US

    Title: SYNAPSE: RANK SELECT OPERATION BETWEEN AN XIO INTERFACE AND A DOUBLE DATA RATE INTERFACE
    11/23/2010 Issued as Patent 7840744 in US

    Title: MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK
    12/16/2008 Issued as Patent 7467277 in US
    07/20/2010 Issued as Patent 7761682 in US

    Title: OPTIMIZING DATA BANDWIDTH ACROSS A VARIABLE ASYNCHRONOUS CLOCK DOMAIN
    02/23/2010 Issued as Patent 7669028 in US

    Title: MEMORY CONTROLLER CAPABLE OF LOCATING AN OPEN COMMAND CYCLE TO ISSUE A PRECHARGE PACKET
    05/27/2008 Issued as Patent 7380083 in US

    STRUCTURE OF SEQUENCERS THAT PERFORM INITIAL AND PERIODIC CALIBRATIONS IN A MEMORY SYSTEM
    07/07/2009 Patent 7558908 in US

    SYSTEM AND METHOD FOR TIMING PARAMETER CONSTRAINTS TO SIMPLIFY XDR DRAM CONTROLLER DESIGN

    MEMORY CONTROLLER TO UTILIZE DRAM WRITE BUFFERS
    07/10/2012 Patent 8219745 in US

    REUSE OF FUNCTIONAL DATA BUFFERS FOR PATTERN BUFFERS FOR XDR DRAM
    05/27/2008 Patent 7380052 in US
    04/12/2011 Patent 7925823 in US

    METHOD AND APPARATUS FOR MANAGING WRITE-TO-READ TURNAROUNDS IN EARLY READ AFTER WRITE MEMORY SYSTEM
    01/22/2008 Patent 7321950 in US

    MANAGING WRITE-TO-READ TURNAROUNDS IN AN EARLY READ AFTER WRITE MEMORY SYSTEM
    02/03/2009 Patent 7487318 in US
    07/06/2010 Patent 7752379 in US

    DEFERRING REFRESHES DURING CALIBRATIONS IN MEMORY SYSTEMS
    04/08/2008 Patent 7356642 in US

    METHOD AND APPARATUS TO AVOID COLLISIONS BETWEEN ROW ACTIVATE AD COLUMN READ OR COLUMN WRITE COMMANDS
    01/22/2008 Patent 7321961 in US

    METHOD AND APPARATUS FOR SCALING INPUT BANDWIDTH FOR BANDWIDTH ALLOCATION TECHNOLOGY
    02/09/2010 Patent 7660246 in US

  • The Presidents Volunteer Service Award - 2013

    -

    For volunteer service

  • The President's Volunteer Service Award

    National & Community Service

    For volunteer service in the community mentoring and teaching youth.

  • Ideas Published

    -

    Title: SMARTER PLANET CONTROL: METHOD AND APPARATUS FOR USING CELLPHONE FOR REMOTE SURVEILLANCE AND CONTROL
    03/18/2011 : Published

    Title: SMARTER PLANET TELECONFERENCING: SMARTPHONE HOLDER FOR TELECONFERENCING PROVIDING REMOTE ROTATE AND TILT CONTROL
    03/18/2011 : Published

    Title: FLASH DWELL TIME COMPENSATION FOR SOLID STATE DRIVE RELIABILITY MANAGEMENT
    09/03/2010 : Published

    Title: FLASH DWELL TIME COMPENSATION FOR SOLID STATE DRIVE PERFORMANCE…

    Title: SMARTER PLANET CONTROL: METHOD AND APPARATUS FOR USING CELLPHONE FOR REMOTE SURVEILLANCE AND CONTROL
    03/18/2011 : Published

    Title: SMARTER PLANET TELECONFERENCING: SMARTPHONE HOLDER FOR TELECONFERENCING PROVIDING REMOTE ROTATE AND TILT CONTROL
    03/18/2011 : Published

    Title: FLASH DWELL TIME COMPENSATION FOR SOLID STATE DRIVE RELIABILITY MANAGEMENT
    09/03/2010 : Published

    Title: FLASH DWELL TIME COMPENSATION FOR SOLID STATE DRIVE PERFORMANCE MANAGEMENT
    09/02/2010 : Published

    Title: SYNAPSE: METHOD FOR CONVERTING XDR WRITE MASK TO DDR2/3 WRITE MASK
    05/16/2006 : Published

    Title: SYNAPSE: INITIALIZING ECC WHEN USING AN XDR CONTROLLER W/ DDR2/3 BRIDGE CHIP
    04/25/2006 : Published

    Title: HARDWARE SUPPORT OF CHARACTERIZATION OF AN XDR MEMORY
    01/24/2006 : Published

    Title: STI:OPTIMIZING COMMAND SELECTION FOR XDR MEMORY SYSTEMS
    06/07/2005 : Published

    Title: STI: METHOD FOR TREATING REFRESHES IN AN XDR MEMORY SYSTEM
    01/15/2004 : Published

    Title: STI: CONTROLLING THE NUMBER OF SEQUENCERS AVAILABLE IN AN XDR MEMORY UNIT
    01/08/2004 : Published

  • Bravo! Award: Soma DD1.0 First Time Right

    IBM

    An award for being part of the a chip that had no errors in the silicon. This saved dollars and time.

  • Bravo! Award

    Kathy Papermaster at IBM

    Delivering the force behind: PlayStation3

Languages

  • English

    Native or bilingual proficiency

  • Spanish

    Limited working proficiency

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