Questions tagged [cpu-architecture]
The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller. Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.
cpu-architecture
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Can you have multiple copies of same data in cpu cache
From wikipedia https://en.wikipedia.org/wiki/Cache_coherence
Multiple copies of same data can exist in different cache simultaneously and if processors are allowed to update their own copies freely, ...
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Can false sharing happen in Direct-Mapped Cache?
If each address in memory is directly mapped to deterministic location in cache, cache coherence is not needed because all thread that access share data share the same cache.
Ie. Within the context of ...
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At what point in the interrupt-processing path does device-driver code execute?
I am new to interrupt handlers and device i/o and I have a few questions:
When you load a device-driver, i.e. kernel module, its assembly code is stored in the module-mapping region of the Kernel ...
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While running a piece of driver code on an AMD64 machine, it appears that there are issues related to cache consistency or out-of-order execution
While running a piece of driver code on an AMD64 machine, it appears that there are issues related to cache consistency or out-of-order execution. Are there any experienced engineers who can help ...
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the Perf event issues of hardware prefetcher (all_pf_data_rd and pf_l2_data_rd)
My platform is 2nd generation scalable Xeon, equipped with a non-inclusive cache. I run a series of tests that had the L2 stream prefetcher aggressively prefetching.
I use Perf to monitor performance, ...
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Difference between an 8-bit addressable CPU and an 8-bit CPU [closed]
I was recently given a test and they mentioned that the CPU was an 8-bit addressable one. They wanted me to write a C program that would write a character of arrays to some specific location in the ...
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How does one Compute Fractional Values into Different BCD Codes?
I know the basics of the Gray and 84-2-1 code, for example a value like 5 should be 1011 in 84-2-1
8 4 -2 -1
1 0 1 1
8 - 2 - 1 = 5
whereas in Gray Code it should be 101
101 (binary of 5)
add 1 to MSB ...
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comparing the performance of a x86 processor with gem5
I'm trying to create a gem5 implementation that is close to a x86 processor in terms of performance. However, I'm not sure which statistic I can use to compare the performance of the two.
I was ...
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lmc program division assembly languange
I'm trying to solve this challenge:
create a simple LMC program to determine if a number evenly divides another one:
Input 2 numbers
If they do not evenly divide, then the program outputs 0 and asks ...
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what openOCD does to spike while debugging a program with spike?
My initial aim is to understand how debug mode works to design the debug mode of a CPU. I am following the guidelines of the riscv-isa-sim repo to debug a program. The only difference is creating a ...
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What happens with the store "that lost race" to shared memory in x86 TSO memory model?
I know that x86 processors use TSO memory model and I am curious about one thing. I will explain it through example.
We have two processors (P1 and P2) where P1 stores X=1 to its store buffer and P2 ...
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How exactly x86 processor fetches the first instruction from SPI flash memory
On a x86 processor upon power ON of the system , the first instruction the processor usually execute is at 0xFFFFFFF0 which is called reset vector. Typically this address is in the BIOS or flash ...
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MOESI Protocol: What happens when Owned is dirty and other processors read the line in Shared?
I've been thinking about the "owned" state of the MOESI protocol. So let's say the following situation exists:
P0 has line A in O state.
P1 has line A in S state.
P0 writes to line A in its ...
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How can a weaker memory model prevent slowdown from false sharing?
I have been experimenting with a simple true/false sharing benchmark, which does regular load+increment+write on a pointer. Basically this:
static void do_increments(volatile size_t *buffer, size_t ...
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How does ARM's MTE prevent off-by-one memory errors?
I understand that MTE uses TBI (Top Bit Ignore) feature from ARM, so some of the top 4 bits in a virtual memory address is used to carry the tag for the memory allocation.
But then I'm curious how ...
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