Questions tagged [riscv]
For questions related to RISC-V assembler, compiler specifics and HDL (hardware description language) implementation and use. Note: Questions on hardware implementation will be more appropriate for the electronics engineering site: https://electronics.stackexchange.com
riscv
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format of RISCV instruction encoding in Spike?
In QEMU RISCV instruction sub encoded according to RISCV spec,
where dots represent variable bits, which encode 2 source and 1 destination register indices.
sub 0100000 ..... ..... 000 ..... ...
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1
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CH32V003 Auto-wakeup Window Comparison Value Register problem
I've stumbled upon something I can't understand.
The MCU is CH32V003, RISC-V, RV32E model. The compiler is gcc version 8.2.0 (xPack GNU RISC-V Embedded GCC, 64-bit), supplied by manufacturer. The ...
- 1,260
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RISC V : I don't understand what the GNU assembler does with labels in the .data segment
I am making my own risc V core as a personal project using the RV32I ISA, I am using a Harvard memory architecture meaning I have a program memory that starts at address 0x0 and a separate data memory ...
- 11
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llama run on qemu-riscv64 with and without vector extension
I want to run llama with and without vector extension on qemu in ubuntu. i have the latest riscv toolchain and qemu. when i run the code
$ qemu-riscv64 -L /path/to/sysroot/ -cpu rv64,v=true,vlen=...
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RISC-V assembly: global pointer set to a weird value
I am experimenting with RISC-V assembly language on an emulator (qemu64, ubuntu for RISC-V).
Here is a simple program, its function is to convert the instr string to uppercase, outstr is the resulting ...
- 214
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build the gcc5.4 in riscv, but rising the error that unknown mode 'TF'
I need to use gcc5.4 in riscv cpu.So I have replace the following files, which from this website.
./isl-0.14/config.sub
./mpfr-2.4.2/config.sub
./config.sub
./mpc-0.8.1/config.sub
./libjava/classpath/...
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what openOCD does to spike while debugging a program with spike?
My initial aim is to understand how debug mode works to design the debug mode of a CPU. I am following the guidelines of the riscv-isa-sim repo to debug a program. The only difference is creating a ...
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RVV type for a class member in C++
I would like to use RISC-V vector extension in my C++ application.
I noticed that it is not possible to use RVV types (e.g., "vuint32m1_t") for class members. Compiling with gcc (v13.2.0), I ...
- 33
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Restoring riscv64 machine using a full backup
I have a cluster of riscv machines (LicheePI 4A) whom I want to back up in case something goes terribly wrong and I need to restore them up from scratch but keeping changes made. I am using a hard ...
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Cannot stepi into ecall in xv6
I am on the traps lecture of the 2023 version of the course. Following the instructions here tell me that I can stepi into the ecall instruction and see the jump to trapframe.
This does not seem to ...
- 11
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Writing to qemu RISCV UART using c
I made a helloworld program on RISC-V qemu using the UART using https://popovicu.com/posts/bare-metal-programming-risc-v/ Uros Popovicu's guide in RISC-V assembly. I was wondering how I could write to ...
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GCC Compile-time switch for floating point support?
I am working on some programs for two different riscv processors. One is IMC, and the other is IMFC. I'd like to add a compile switch to my program to block out floating point code for the IMC target ...
- 11
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What's the difference between the addi and li instructions in RISC-V? Which one is more efficient? [duplicate]
I have a simple question regarding the difference between the instruction addi and li.
I'm have a code with this instruction li a2, 20, but this one was recommended instead addi a2, x0, 20.
I would ...
- 394
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Exception RISCV APB
I have a RISC-V core receiving commands from an APB3 interface, and I would like to test the pslverr flag. I noticed that the core hangs when pslverr is received so I probably need to handle it ...
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Converting ARM assembly to RISC-V assembly
I am trying to rewrite this code. It works perfectly for ARM assembly, but I am trying to rewrite it in RISC-V assembly. Here is the ARM code:
.text
.global main
.equ ADD1, 0x40000000
.set ADD2, ...
