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In PCIe base specification document, it is mentioned that

Disabling scrambling is intended to help simplify test and debug equipment...

I am implementing my own custom gen2 PCIe IP in Verilog and I would very much like to skip the scrambling/descrambling for now and may be permanentely to reduce the resources of PCIe IP and also the build time.

What is the effect of disabling the scrambling on PCIe link stability?

So far I have not found any drawback of disabling the scrambling on PCIe link.

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  • \$\begingroup\$ I have not found any drawback of disabling the scrambling on PCIe link. Failing EMC tests would be considered a drawback I think :) Scrambling wasn't added for fun, as you've noticed it's extra work to implement. It's one of the mechanisms used in system design to minimize radiated and conducted peaks and spread the energy around a wider band. If this is going into FPGA then it'll be easy to fix later assuming the FPGA has the resources left to do it. If you want to be selling that IP or putting it into silicon, leaving out scrambling will be an expensive mistake. \$\endgroup\$
    – Kuba hasn't forgotten Monica
    Commented Feb 16 at 7:07
  • \$\begingroup\$ You are correct that it is there for some reason. I totally agree. But for now I am asking for some mathematical explanation or some experimentation that shows this effect I have found graphs showing that energy radiation is reduced by scrambling but not any results without scrambling. \$\endgroup\$
    – Im Groot
    Commented Feb 16 at 7:49
  • \$\begingroup\$ Currently I am implementing it in FPGA only as a Verilog Code. So later on I can focus on scrambling after completing the rest of the IP. \$\endgroup\$
    – Im Groot
    Commented Feb 16 at 7:49

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