Questions tagged [lfsr]
LFSR, or Linear Feedback Shift Register, is a shift register with flip-flops, the values of which may not only depend on the previous flip-flop. LFSR's are often used for pseudo-random generators or CRC calculations.
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What is the effect of disabling the scrambling on PCIe link stability?
In PCIe base specification document, it is mentioned that
Disabling scrambling is intended to help simplify test and debug equipment...
I am implementing my own custom gen2 PCIe IP in Verilog and I ...
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Clarification needed on LFSR and MISR
I’m attempting a question that involves a three stage LFSR and MISR with a CUT. I’ve been trying to solve for 3 hours straight now, I couldn’t confirm my solution; meaning, i don’t know wether it’s ...
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Name and generator for no-repeating-substring bit strings
While solving a different problem I stumbled across an interesting class of bit patterns: a 2n-bit cyclic sequence, all of whose n-bit subsequences are unique. With n=3, for example, the bits ...
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How do I make this LFSR circuit generate random events every time the power is turned on?
I can't make this circuit work as expected and generate random events every time I turn on the power. I have checked NAND gates (IC3B, IC3C) and they generating clock signal with no problem. The only ...
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Why do shift registers (LFSR) use the initial state "all 1"?
In all books about information coding theory, scientists describe shift registers of various configurations, but they always use the initial state "all 1" in any configuration and any bit ...
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How to prevent 7 from displaying in digital dice roller circuit?
Anyone got any ideas on how to prevent 7 from displaying?
There are some cheap ideas that my professor said were bad: one being delaying the clock and the other is ...
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Why use LFSR on this context?
There is a task in Pong chu's fpga prototyping book which is to basically generate a random number from 0 to 15_000 millisecond. I saw someone's code who used LFSR. (ctto owner)
The author used a ...
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How to create a nested for-loop in Verilog?
I try to create a CRC module on Verilog.
The CRC calculating use an LFSR and can be fully-sequential (with two cycles), semi-sequential (with one cycle) or parallel. I have already made sequential ...
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Verilog HDL LFSR
I want to design this circuit using the Verilog HDL.
However, I can't make a feedback part well.
Here is my code.
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