Questions tagged [immediate-operand]
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immediate-operand
103
questions
3
votes
1
answer
63
views
How to get NASM to encode `push` with a sign-extended 16-bit immediate?
When assembling the following with NASM:
BITS 64
push 32767
I get 68 ff 7f 00 00. This is interesting to me, since this is the 32b encoding (push dword). Any ideas why it doesn't resort to the 16b ...
- 69
1
vote
0
answers
66
views
Assembling with gcc gives error operand type mismatch for `cmp' for some integers, not others
This is a weird one. I'm using gcc to assemble a program and I want to know if the value in register rsi fits in 32 bits, so I use this instruction:
cmpq $0xffffffff, %rsi
I get back an error that ...
- 11
2
votes
0
answers
74
views
Understanding Bitmask Immediates in ARM64 Assembly [duplicate]
I'm currently learning ARM64 assembly and I'm having trouble understanding how bitmask immediates are implemented and validated. I've read that ARM64 has specific rules for what constitutes a valid ...
- 21
2
votes
1
answer
74
views
GNU as: when to use '$'
After a long time I have to use the GNU assembler again. Ever since I had trouble with the '$'.
The manual just says:
3.6.2.1 Integers
A decimal integer starts with a non-zero digit followed by zero ...
- 61
0
votes
1
answer
88
views
Do I need to split up a very large number to move it into a 32-bit register in ARM64
I am trying to write a program in ARMv8 AArch64 (ARM64 if you prefer) and I want to move a very large number into a 32-bit register. From what I know, the correct format is
mov w20, 36383899
However, ...
user16342430
0
votes
1
answer
61
views
Is there a set format on how immediates are shown in RISC-V assembly?
I'm working on parsing RISC-V assembly, and am working on parsing immediates. Using the LUI instruction as an example, I'm seeing examples which write it like lui t0, 0, and examples which write it ...
- 753
0
votes
1
answer
518
views
How do I concatenate immediate value of type B RISC-V instruction?
I have the following binary from a RISC-V instruction that I need to decode: 11111110000011100001100011100011
Using the RISC-V reference card, I know the following information:
Its opcode is 1100011, ...
- 305
2
votes
1
answer
174
views
Is there an inline assembly constraint for 32-bit immediate for x86-64
Is there a constraint for x86-64 that is similar to the "i" constraint, but that only matches when the operand value fits in a 32-bit signed immediate?
For the function shown below, I would ...
- 12.2k
0
votes
0
answers
73
views
ARMv8-a GNU assembler error : immediate out of range at operand 3 [duplicate]
I am having trouble performing logical instructions on the ARMv8-a architecture.
for example, "and x13, x13, #0x0000CCCC0000CCCC" or "and x13, x13, #0x0A0A0A0A0A0A0A0A" results in ...
- 1
0
votes
1
answer
57
views
Visual Studio 2022, Can I control how the immediate values are generated for arm64 compilation?
When I have the following code:
int value2 = 0x11223344;
The VS2022 compiler (arm64) generates:
StarFunction PROC
...
ldr w8,|value_label|
...
...
...
ret
|value_label|
DCD ...
- 359
1
vote
0
answers
302
views
arm asm: Value too large for field with numeric literal for :upper8_15:
GNU ARM assembler supports prefixes to extract group of bytes from a relocation value https://sourceware.org/binutils/docs/as.html#ARM_002dRelocations
On ARMv7m and later, the low/high 16 bit ...
- 4,225
3
votes
1
answer
424
views
Force arm64 gcc use instruction to construct double floating point number, no .rodata section
ARM64 instructions are 32-bit long, so normally a data section is used to store literals if one wants to use a 64-bit floating point constant number.
However, I found in some cases where AArch64 gcc ...
- 53
0
votes
0
answers
261
views
MIPS assembly `addi` instruction, how is a hexadecimal immediate interpreted? [duplicate]
there is a difference between those two instructions?
addI $12,$1,0x0000ffff
vs
addI $12,$1,0xffff
I need to know what is the value of
$12 after those instruction :
lui $1,0xffffff00
addi $12,$1,...
- 11
4
votes
1
answer
614
views
NASM Intel 64-bit mode: why does 32-bit constant 0xffffffff cause "warning: signed dword value exceeds bounds"
In NASM (2.14.02), the instruction add rbx, 0xffffffff leads to
warning: signed dword value exceeds bounds [-w+number-overflow]
I'm aware that arithmetic-logic operations in 64-bit mode only accept ...
- 1,285
1
vote
1
answer
80
views
What is SignImm in Branch Target Address formula context? (BTA)
I would like to know what is SignImm in the following formula:
BTA = Branch Target Address = PC(old) + 4 + (SignImm << 2)
I have read that it is the address distance between the old PC + 4 and ...
- 305