Questions tagged [instruction-encoding]
The instruction-encoding tag has no usage guidance.
instruction-encoding
113
questions
4
votes
0
answers
59
views
Why does Intel x86 manual use +rd instead of +ro or +rq for 64-bit registers?
The description of the PUSH instruction in the Intel manual (PDF, Volume 2, Chapter 4.3, PUSH) contains the line 50+rd PUSH r64. It seems +rd is used throughout most of the instruction descriptions ...
- 118
3
votes
1
answer
63
views
How to get NASM to encode `push` with a sign-extended 16-bit immediate?
When assembling the following with NASM:
BITS 64
push 32767
I get 68 ff 7f 00 00. This is interesting to me, since this is the 32b encoding (push dword). Any ideas why it doesn't resort to the 16b ...
- 69
2
votes
1
answer
75
views
ModR/M Historical Notation /0.../7
While learning about x64, I struggled to understand some notations in the intel manual.
Let's look at 0xC7 MOV:
opcode
instruction
Op/Enc
Description
C7 /0 iw
MOV r/m16, imm16
MI
Move imm16 to r/m16....
- 4,349
2
votes
1
answer
83
views
Trying to understand object code for "MOV AX,BX", am I dumb or is the textbook bad?
EDIT: Based on the answers and comments, it appears both the book and I are correct. BUT IMHO the book did a poor job of explaining the example, I mean instead of something like "For this ...
- 21
0
votes
1
answer
37
views
Why LI becomes LBU opcode after MIPS assembler
I'm trying to assemble code for MIPS R2000 (MIPS I ISA).
I'm using LI pseudo instruction to initiate a register. After running the assembler on the following code:
li $v1, 1
The binary .text ends up ...
- 355
2
votes
0
answers
71
views
Can NASM be forced to generate mov with offset of 0?
My question
I have tried using NASM's strict keyword and -O0 to inhibit it from turning mov dword [rdi+0], 0xab into mov dword [rdi], 0xab, but haven't been successful. My hunch is that the +0 gets ...
- 347
2
votes
2
answers
96
views
Machine code layout in the memory - Intel x86
I was asked to convert the following machine code to assembly in Intel syntax:
0x421a0770: 0D 00 3D 77
0x421a0774: AC 3D 11 2A
0x421a0778: 96 AB 77 04
0x421a077c: 90 2D 0D ...
- 31
3
votes
1
answer
87
views
Encoding "MOV EAX, moffs32" on x86-64
I have stumbled across the "MOV EAX, moffs32" instruction while trying to understand x86-64.
As far as I can tell, this instruction would get encoded (with an moffs32 of 0x12345678) to just ...
- 686
1
vote
1
answer
74
views
In shift left instruction, why is rt used as source register instead of rs?
In a shift left / shift right instruction, the rt is used as source register. Is there any reason why rt is used as source register, instead of rs ?
I saw some similar question answered "It is to ...
- 13
0
votes
1
answer
29
views
What's the difference between the '-' and '.' in the decode of RISCV instructions in QEMU?
The instructions of RISCV are decoded into 32 bits. When some part of the decoded instruction is required from the input, dot '.' is used to server as the placeholder for each bit. However, there're ...
- 11
0
votes
1
answer
107
views
x86_64 primary opcode byte categorization
I'm in the process of writing an x86_64 disassembler, to get a better understanding of the assembly-encoding rules. I got a working version, and I understand most things about prefixes, modR/M and so ...
- 1,077
3
votes
0
answers
69
views
Breakdown MOV instruction on Intel 64 compatibility mode
I'm checking the assembly code for a MOV instruction on Intel 64 (long) compatibility sub-mode.
For a mov edx,408ACB77 the debugger (x32dbg for Windows) shows
BA 408ACB77
From Intel 64 SDM this MOV ...
- 179
0
votes
0
answers
130
views
Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
Confused about instruction encoding supported by my core (ie. T1, T2, etc)
Having the STM32F0 series Cortex-M0 programming manual, I found that
https://www.st.com/resource/en/programming_manual/pm0215-...
- 1,599
0
votes
1
answer
518
views
How do I concatenate immediate value of type B RISC-V instruction?
I have the following binary from a RISC-V instruction that I need to decode: 11111110000011100001100011100011
Using the RISC-V reference card, I know the following information:
Its opcode is 1100011, ...
- 305
4
votes
0
answers
62
views
Are these push r16 encodings correct under 64BIT mode?
About push wordregister(r16) under 64BIT mode of Intel x86_64 CPU.
In B-28, Vol. 2D,
APPENDIX B, INSTRUCTION FORMATS AND ENCODINGS,
Intel Combined Manual PDF,
Order Number: 325462-080US, June 2023.
...
- 87