Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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Why are PCIE's coupling capacitors so large
I was looking at the PCIE specification, and I don't understand the
requirement for coupling capacitors. For 2.5GT/s, the standard requires
AC coupling capacitors of 75nF to 265nF. I tried to ...
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What is the utility of the reference clock in PCI express?
I understand that PCI express is a serial connection with clock embedded with the signals. So, what is the utility of the reference clock signal? What is it used for?
Does the reference clock have to ...
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Pin dimensions on PCI Express card edge
I can see this as being 50/50 between here and Eng.SE, so I decided to ask here as it deals with the PCI Express standard.
I'm attempting to create a library of PCI Express card edge footprints in ...
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Does PCIe hotplug actually work in practice?
I've got into a discussion in the comments of https://security.stackexchange.com/questions/109199/is-physical-security-less-important-now-for-securing-a-server?noredirect=1#comment194327_109199
The ...
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PCIe, diagnosing and improving an eye diagram
I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector).
The root ...
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Is it possible to only utilise SMBus on PCI Express 1X?
According to the Wikipedia page on PCI Express, the PCI-e 1X slots have 18 pin positions on two lanes (so 36 pins) and positions 5-9 represent SMBus and JTAG.
I'd like to hook up a µC as an ...
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Why doesn't PCIe and similar signaling systems use full-duplex links?
I'd like to get more PCIe bandwidth for GPU compute applications. It occurred to me that PCIe bidirectional links are really dual simplex (a pair of unidirectional links). That means if there's no ...
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What is the usable area (for connectors) of a PCI Express card bracket?
I have a number of awkwardly shaped connectors that I need to cram into a single PCI Express slot metal bracket without any of them colliding with the host PC case's metalwork. The connectors are a ...
user98663
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Does this PCIe routing look ok?
It is the first time for me to design a PCB with a PCIe bus. My first design failed, the bus is not working!
Tom helped me in this question and instructed me how to correctly route a high speed bus - ...
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AC coupling on PCIe layout
I'm working on a layout in which two chips connect to each other through a 1x PCIe bus. The two chips are on one board.
One of the chips is the Xilinx Spartan6 LX75T so I've been working with the ...
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Ethernet controller not recognized on PCIe bus
I designed a carrier board for this SOM: https://wiki.solid-run.com/doku.php?id=products:ibx:documents
As I need a second Ethernet port I added an Intel I217 Ethernet controller. Unfortunately it ...
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Can i run several links through single pcie x8 connector?
I want to use PCIe with four to eight remote devices, and preferably to avoid PCIe switch. In PCIe connector i can see enough lanes for that, but i definitely don't want to use eight separate cards ...
user76844
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How PCIe can tranmit data at 2.5 GTps?
Serial transceiver for PCIe is using Reference clock of 100MHz. Then how data transfer at the rate of 2.5 GTs is possible?
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How does PCIe Endpoint device advertise the BAR memory space requirement to the host?
In many PCIe training material, there is details walkthrough on how the BAR is being programmed.
I think I probably can understand some portion of that, but somehow there is a missing pieces that I ...
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Anyone knows how X86 platform set the PCIe bifurcation at boot up?
I got a question about the PCIe bifurcation setting when booting up in X86 system.
Normally, we can set the PCIe controller to be X16, two X8, or four X4 in the UEFI shell menu. However, there is an ...
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