Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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Setting up T2080 to FPGA PCie DMA
I'm doing an FPGA design using a T2080 MPC interfacing to an Altera Cyclone V FPGA. The goal is to use my FPGA to pump 2 other FPGAs on the same board.
I need to create a scheme that allows the ...
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Designing a U.2 to M.2 NVMe adapter
I'm considering designing my own U.2 to M.2 converter card to make use of the four U.2 (PCIe 3.0 x4) connectors on my motherboard. Commercial products are available for doing this type of conversion, ...
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Is compliance testing necessary for PCIE3.0 if the SOC and Wi-Fi chipset is on the same board?
In my product, PCIe is just used for data transmission between SOC and Wi-Fi chipset. It's not used for any other purpose. Is compliance testing necessary for this scenario?
What type of SI ...
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Studying the PCIe/CXL/CCIX internals at home
Could anybody recommend me a good starting point for self-studying the PCIe internals?
I imagine some kind of an FPGA-based course, covering PCIe endpoint, root complex and switching functionalities. ...
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M.2 to mini PCIE
I have an SBC with the following configuration on the M2 port
If I require a mini PCIE device is it sufficient to make a breakout board and match pin to pin? We have a pcb engineer to handle the high ...
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Is it bad to load one rail of a power supply vastly more than the other?
I am trying to modify a Delta DPS-400AB-17 server 1U power supply to support a desktop motherboard and graphics card. The power supply has an 8 pin 12V EPS connector attached to a 21A 12V (252W) rail. ...
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When is a PCIE endpoint/card powered?
At what point in host boot process, does a PCIE endpoint get powered ?
Is it powered as soon as the host/PC starts booting or when it starts the enumeration process ?
References would be appreciated....
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Why DMI instead of a PCIe link
In some Intel chipsets the CPU is connected to the Platform Controller Hub (PCH) by a link called Direct Media Interface (DMI). Based on what I found when researching about it, It's a link very ...
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What is the typical NVME SSD abrubt shutdown reaction time for a CC.SHN event until power loss?
The NVME standard under "7.6.2 Shutdown" defines the procedure for an abrupt shutdown event:
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Trying to replace laptop's dGPU with eGPU. Is it possible?
I try to replace GT 840 dPGU with eGPU on V3-572PG mainboard for which I have circuit and boardview.
I'd desoldered dGPU. Then after study of boardview I could easy match pins from dGPU socket to pins ...
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What are these PCIe connectors that are slightly larger than SFF-8653 8i?
I have some computer motherboards that ware evidently a special-order for the ASRock Rack because the vendor does not have the model listed on their website, and when I contacted them they said they ...
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Can I connect one PCIE_CLKREQ# pin from SoC to two different devices?
In my design, I'm using VL805 USB 3.0 Host Controller which takes 1 lane of PCIe and outputs 4 ports of USB3.2 Gen 1.
The platform which I'm building is based on AMD V3000 CPU.
My question is, if ...
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Remapping a PCI(e) device when another core is accessing the device
According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)?
If not, ...
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Does my PCIe platform support CLKREQ#?
I succeeded entering ASPM L1.1 and L1.2 for my device. After entering ASPM L1.1 or L1.2 and trying to initiate to exit from Host side, I saw some hosts that are:
• Able to initiate an exit from ASPM ...
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Unable to Identify VL805 device
I have designed a PCIE to USB3 converter device that is based to VIA LABS VL805 Q6 Chip.
My problem that I can't recognize the VL805 chip in Linux, using the command "lspci":
here is the ...
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