Skip to content

Issues: chipsalliance/chisel

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
306 Open 727 Closed
306 Open 727 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Get better test coverage code improvement
#486 opened Feb 6, 2017 by ducky64 3.3.0
Source info support for libraries is something that needs more thought and discussion. feature request Feature New feature, will be included in release notes
#601 opened Apr 28, 2017 by ucbjrl 3.X
Feature discussion | Generating SystemVerilog assertions from Chisel
#984 opened Jan 15, 2019 by anmolsahoo25
Notification on moving to WireDefault
#1001 opened Jan 25, 2019 by schoeberl
API supports for ValidIO
#1055 opened Mar 29, 2019 by zqxkb7fh
Investigate behaviour of Vec(Record()) and nested Vec code improvement
#1074 opened Apr 19, 2019 by edwardcwang
Define isLit for Bundle Literals
#1084 opened Apr 27, 2019 by ducky64
BlackBoxUtils use a BlackBox self-type, should be BaseBlackBox?
#1108 opened Jun 12, 2019 by seldridge
Space in setTargetDirName() causes Verilator to fail
#1113 opened Jun 24, 2019 by oharboe
Esoteric Reverse
#1200 opened Oct 1, 2019 by seldridge
Add stacked source locators
#1219 opened Oct 25, 2019 by bodidebnath
Better error message for Vec mono-connected to Seq
#1220 opened Oct 28, 2019 by jackkoenig
chisel3.Driver.execute seems to emit anno file after FIRRTL invocation now
#1221 opened Oct 28, 2019 by jackkoenig
@seldridge
Bad error message for switch(){is()} if multiple is() with same value.
#1233 opened Nov 7, 2019 by Martoni
Make literal handling consistent and reliable for FixedPoint and Interval and others bug Feature New feature, will be included in release notes
#1272 opened Dec 10, 2019 by chick 3.3.0
@chick
Maybe adding chisel3.Driver.apply()
#1368 opened Mar 4, 2020 by schoeberl 3.3.x
Support $ in port names bug
#1391 opened Mar 28, 2020 by jackkoenig 3.3.x
Chisel and Treadle need an elegant Plusargs mechanism feature request
#1396 opened Apr 1, 2020 by davidmlw 3.3.x
CloneModuleAsRecord needs a macro
#1478 opened Jun 18, 2020 by seldridge
Does chisel plan to support full-featured SVA?
#1508 opened Jul 8, 2020 by MichaelYuan89
Printable should adopt a f"-like handling of %
#1522 opened Jul 25, 2020 by jackkoenig
Add CONTRIBUTING.md
#1559 opened Aug 20, 2020 by jackkoenig
Vec.reduceTree leads to java.lang.OutOfMemoryError
#1576 opened Sep 2, 2020 by zhangkunta
Why does FixedPoint get interpreted as Double when printing?
#1588 opened Sep 10, 2020 by Quarky93
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2 bug
#1592 opened Sep 18, 2020 by jackkoenig
ProTip! Mix and match filters to narrow down what you’re looking for.