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Remove implicit width truncation / Don't repeat Verilog's assignment issue in Chisel
strict-semantics
Proposals for stricter semantics
#1163
opened Aug 22, 2019 by
schoeberl
ChiselSim improvements to close the gap to chiseltest
#4203
opened Jun 21, 2024 by
carlosedp
6 tasks
Better documentation of An issue whose fix is simple. Perfect for a new developer wanting to get involved!
:=
vs <>
good first issue
#2087
opened Aug 26, 2021 by
mwachs5
[RFC] New Testers Proposal
API Modification
Feature
New feature, will be included in release notes
Request For Comment
loadMemoryFromFile() should place readmemh() inline for better compatibility
#1293
opened Jan 3, 2020 by
antonblanchard
[RFC] Formalize support for IP-XACT
Feature
New feature, will be included in release notes
release issue
DontCare does not support Clocks
bug
code improvement
feature request
Feature
New feature, will be included in release notes
Memory with write masks result in confusing layout and readmemh() behaviour
bug
#1289
opened Dec 31, 2019 by
antonblanchard
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