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Firtool error occurs when looking up parameters from a definition of a Module with reset
#4292
opened Jul 19, 2024 by
unlsycn
updated Jul 19, 2024
Proposal for Verification IR with reset
#4282
opened Jul 17, 2024 by
poemonsense
updated Jul 17, 2024
SVSim fails when pokeing and incrementing clock in loop
#4281
opened Jul 16, 2024 by
HakamAtassi
updated Jul 16, 2024
API for specifying customized transforms in ChiselStage (and dependencies?)
#4280
opened Jul 16, 2024 by
poemonsense
updated Jul 16, 2024
Pass Chisel information to firtool to generate debug information for the Tywaves project
#4015
opened Apr 19, 2024 by
rameloni
updated Jul 11, 2024
3 of 4 tasks
Mixed-masked/unmasked-port ReadSyncMem is generated incorrectly when "--repl-seq-mem"
#3278
opened May 14, 2023 by
zhutmost
updated Jul 11, 2024
Please make some classes in simulator package public for simulator customization.
#4240
opened Jul 2, 2024 by
zhutmost
updated Jul 2, 2024
asUInt packing inconsistent for Bundles with type parameters
bug
#4223
opened Jun 27, 2024 by
maxbjurling
updated Jun 27, 2024
ChiselSim tests runs orders of magnitude slower than chiseltest
#4207
opened Jun 21, 2024 by
carlosedp
updated Jun 27, 2024
BoringUtils + when/layer/region produces invalid FIRRTL
#4108
opened May 29, 2024 by
dtzSiFive
updated Jun 26, 2024
Chisel chokes on using elements of an unbound Aggregate as elements of a Record
#4215
opened Jun 24, 2024 by
jackkoenig
updated Jun 25, 2024
Module initialization test fails with ChiselSim while worked on chiseltest
#4214
opened Jun 24, 2024 by
carlosedp
updated Jun 24, 2024
[ChiselSim] ChiselEnum does not provide peek/poke methods and user-friendly API
#4208
opened Jun 23, 2024 by
carlosedp
updated Jun 24, 2024
ChiselSim improvements to close the gap to chiseltest
#4203
opened Jun 21, 2024 by
carlosedp
updated Jun 23, 2024
6 tasks
Incorrect direction for mixed specified and unspecified directionality
#4204
opened Jun 21, 2024 by
jackkoenig
updated Jun 21, 2024
Modules with
chisel3.experimental.Analog ports generate error using ChiselSim
bug
#4202
opened Jun 21, 2024 by
carlosedp
updated Jun 21, 2024
loadMemoryFromFile seems not work in chisel6.2.0
#3961
opened Apr 2, 2024 by
yongruifang
updated Jun 21, 2024
It would be nice if ProbeValues of Literals would automatically expand widths
#4174
opened Jun 13, 2024 by
jackkoenig
updated Jun 13, 2024
Probes should print more information about why types are non-equivalent
#4173
opened Jun 13, 2024 by
jackkoenig
updated Jun 13, 2024
Source line + carat for errors should work for Scala CLI Example
#4172
opened Jun 13, 2024 by
jackkoenig
updated Jun 13, 2024
Calling .pad on Bool results in requirement failure with no explanation
#4162
opened Jun 11, 2024 by
jackkoenig
updated Jun 11, 2024
Calling .asUInt on a Bool returns the Bool itself (rather than a true UInt)
#4163
opened Jun 11, 2024 by
jackkoenig
updated Jun 11, 2024
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