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Issues list

Negedge-triggered SRAMs feature request Feature New feature, will be included in release notes
#736 opened Dec 13, 2017 by ccelio updated Mar 2, 2018
4 of 9 tasks
3.X
4
Source info support for libraries is something that needs more thought and discussion. feature request Feature New feature, will be included in release notes
#601 opened Apr 28, 2017 by ucbjrl updated Mar 5, 2018 3.X
Add other operations to Width class Feature New feature, will be included in release notes
#644 opened Jul 10, 2017 by da-steve101 updated Mar 9, 2018 3.X
1
API For Tagging Signals
#609 opened May 10, 2017 by jackkoenig updated Mar 16, 2018 3.3.0
7
Blackbox IO doesn't actually "exist" code improvement
#633 opened Jun 26, 2017 by ducky64 updated Apr 19, 2018 3.X
2
Tests fail without warning when Verilator not installed
#906 opened Oct 9, 2018 by mehnadnerd updated Oct 12, 2018
2
Chisel's IR is public API Modification code improvement
#414 opened Dec 15, 2016 by jackkoenig updated Dec 17, 2018 3.3.0
@jackkoenig
6
Add simulation logging library feature request Feature New feature, will be included in release notes
#435 opened Jan 11, 2017 by sashimi-yzh updated Dec 17, 2018 3.X
3
Get better test coverage code improvement
#486 opened Feb 6, 2017 by ducky64 updated Dec 17, 2018 3.3.0
Backend-dependent inline blackbox code improvement feature request Feature New feature, will be included in release notes
#519 opened Feb 21, 2017 by ducky64 updated Dec 17, 2018 3.3.0
1
Analog type does not allow static addressing of sub-wires feature request Feature New feature, will be included in release notes
#536 opened Feb 27, 2017 by jwright6323 updated Dec 17, 2018 3.3.0
@jackkoenig
3
Digital Top with Analog Black Box feature request
#525 opened Feb 23, 2017 by shunshou updated Dec 17, 2018 3.X
8
[RFC] Tagged Unions
#927 opened Nov 5, 2018 by hngenc updated Dec 18, 2018 3.X
4
Request for a NotSynthesized annotation on a per signal basis. feature request
#886 opened Sep 8, 2018 by ccelio updated Dec 18, 2018 3.X
2
[RFC] New Testers Proposal API Modification Feature New feature, will be included in release notes Request For Comment
#725 opened Dec 6, 2017 by ducky64 updated Jan 1, 2019 3.3.0
54
Feature discussion | Generating SystemVerilog assertions from Chisel
#984 opened Jan 15, 2019 by anmolsahoo25 updated Jan 15, 2019
Notification on moving to WireDefault
#1001 opened Jan 25, 2019 by schoeberl updated Jan 25, 2019
[RFC] Bundle and Vec .Lit and .Wire
#1005 opened Jan 26, 2019 by ducky64 updated Jan 26, 2019
2
Operations returns an OpBinding value regardless of whether all operand is literal or not
#1007 opened Jan 28, 2019 by Soya-Onishi updated Jan 29, 2019
5
API supports for ValidIO
#1055 opened Mar 29, 2019 by zqxkb7fh updated Apr 2, 2019
Investigate behaviour of Vec(Record()) and nested Vec code improvement
#1074 opened Apr 19, 2019 by edwardcwang updated Apr 19, 2019
Bit Slice with (start, length) instead of (start, end)
#1081 opened Apr 23, 2019 by grebe updated Apr 23, 2019
1
Define isLit for Bundle Literals
#1084 opened Apr 27, 2019 by ducky64 updated Apr 27, 2019
[RFC] Add standalone asyncqueue librarys to experimental.
#1067 opened Apr 14, 2019 by sequencer updated Apr 30, 2019
1
[RFC] Warning/Error if CDC not managed correctly
#1085 opened Apr 30, 2019 by Martoni updated Apr 30, 2019
2
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