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suggestName does not work for IO ports : should error not ignore
#2920
opened Jan 5, 2023 by
zhutmost
[chisel-circt] CIRCT phase incorrectly uses removed firtool option
-blackbox-memory
#2914
opened Dec 28, 2022 by
seldridge
ShiftRegister implementation using SyncReadMem to support SRAM-based Shift Registers
#2889
opened Dec 13, 2022 by
milovanovic
Provide a way to normalize directions to distinguish between module ports and child module instance ports
#2884
opened Dec 10, 2022 by
sterin
Chisel sometimes emits bulk connects when it should blast the connection apart
#2858
opened Nov 22, 2022 by
jackkoenig
Cause: chisel3.internal.ChiselException: Error: attempted to instantiate a Module without wrapping it in Module()
#2848
opened Nov 15, 2022 by
pxs7
MonoConnect's canBulkConnectAggregate sinkCanBeDriven check isn't right
#2824
opened Nov 3, 2022 by
mwachs5
Inconsistent/Misleading error messages for illegal ReferenceTargets
#2778
opened Oct 14, 2022 by
mwachs5
Reversing order of arguments to bit extraction gives terrible error message
#2762
opened Oct 5, 2022 by
jackkoenig
Constraint Mux1H to provide deactivated output when given a zero-hot selector.
#2637
opened Jul 21, 2022 by
nicmcd
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