Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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Will a 4 lane PCIe device work if plugged into a PCIe socket the only 1 lane electrically connected
I am designing a motherboard that uses a SMARC format plugin card for the CPU. This card is based on an Intel Atom x6413E CPU. The SMARC CPU card has various interfaces available, including USB2.0, ...
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Wiring VGA card to act as PCIe host?
Is it possible to wire a graphics card to act as a PCIe host controller? I mean, assuming the firmware is also rewritten, is there anything in terms of hardware (EE) that prevents me from using a GPU ...
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How does PCIe Endpoint device advertise the BAR memory space requirement to the host?
In many PCIe training material, there is details walkthrough on how the BAR is being programmed.
I think I probably can understand some portion of that, but somehow there is a missing pieces that I ...
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NVIDIA Jetson custom carrier board does not booting when PCIE device is attached. How can I track the problem?
I have designed an custom NVIDIA Jetson carrier board based on P3449-B01 Jetson Nano Carrier Board reference design by NVIDIA.
The carrier board is working fine, the linux is booting up, however when ...
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Communication between two ARM chips over PCI-e
I have a LX2162A CPU from NXP (datasheet is here), and 2 I.MX8.Quad, also from NXP (Datasheet is here)
My goal
My goal is to design a NUMA enabled system. A single instance of a mainline linux will ...
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PCIE Wake signal connection
I'm trying to connect a PCIE to USB 3.0 controller by Renesas UPD720201 but I'm not very sure how I should to connect with PCIE Raspberry Compute 4 PCIE lines.
On the Renesas guide design they connect ...
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Are AC coupling capacitors required for the Clock lanes in the PCIe spec
I'm working on implementing a PCIe 2.0 x2 system on a with a Xilinx Ultrascale. Reading through the PCIe 2.0 specification it requires 75-200nF AC coupling capacitors on the TX lines coming from the ...
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How important is a PCIE_PEG_TXN pin on a motherboard?
I managed to break the PCIE_PEG_TXN 2 pin on my motherboard according to this pin layout: https://sector.biz.ua/docs/lga-775-1150-1151-1156-1155-1366-2011-pinouts/s1200_1.png I am curious if it is ...
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Create a transmission through PCIE lines or Ethernet lines
I'm working on a data transmission design.
I would like to create a data transmission from a Raspberry Compute Module 4, but I don't know what is the better way to do that. A USB-C is required, and ...
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PCIe PRST pin functionality at M.2 connector (B) with SATA device (reboot detection)
M.2 connector type (key B) support PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus.
I want to use SATA interface with my device, but I need to detect the reboot of the host ...
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PCIe pin out (point of view)
I made a board and I would like to connect it to a PC with a PCIe edge connector. The PC will be the root complex (master) and my board the endpoint (slave).
I have a question about the pinout of the ...
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Confirm if Dell PowerEdge R720 Power port mixes pin layout/wiring of PCIE and keying/shape of CPU port
This cable 1 works fine to power a PCIE accelerator device (Intel N3000-N FGPA PAC) on Dell PowerEdge R720. The power connector that plugs into the riser seems to break power cable/port standards/...
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Termination of unused mini PCIE lines on a USB only device
We're designing a USB only mini PCIE card and I'm trying to work out if it is required, or at least good practice, to terminate the high speed lines that are unused on the mini PCIE card. I can't find ...
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What limit the pci-e splitting on this case?
I am trying to understand the PCI-E principles but I miss something.
The reason why I need to understand that is because I working on a project that involve a lot of SATA HDD to be connected to one ...
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Is it possible to leave certain pins of an m.2 slot not connected to their PCIe lanes on a processor?
We are in the process of making a custom board for a System On Module. The System On Module exposes 4 PCIe Gen 2 lanes on its SODIMM pinout. As per our requirement, we are planning on having a WiFi/...
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